From: Chao-ying Fu Date: Mon, 7 Oct 2013 18:02:47 +0000 (+0000) Subject: 2013-10-07 Chao-ying Fu X-Git-Tag: binutils_latest_snapshot~138 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=45099dfad225994154148d0fef2ff98f9e0d4e34;p=external%2Fbinutils.git 2013-10-07 Chao-ying Fu * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ae22ba9..901e590 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2013-10-07 Chao-ying Fu + + * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0. + 2013-09-30 H.J. Lu * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index fa6efb5..c5733d4 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -586,12 +586,12 @@ const struct mips_opcode micromips_opcodes[] = {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, {"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_1|RD_C0, 0, I3, 0, 0 }, {"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I3, 0, 0 }, -{"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, -{"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, {"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, -{"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, {"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I3, 0, 0 },