From: Kim, HeungJun Date: Wed, 20 May 2009 08:12:26 +0000 (+0900) Subject: [S5PC100] add gpio generic header X-Git-Tag: s5pc110_universal_support~321 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=44b03e21082364e89dabbf97a128f29313ccdf92;p=kernel%2Fu-boot.git [S5PC100] add gpio generic header --- diff --git a/include/s5pc100.h b/include/s5pc100.h index c60403e..3266a92 100644 --- a/include/s5pc100.h +++ b/include/s5pc100.h @@ -990,7 +990,6 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) - #if defined (__S5PC100_H__) /* @@ -1003,77 +1002,670 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) #include -#define S5C_ADDR_BASE (0xe0000000) -#define S5C_ADDR(x) (S5C_ADDR_BASE + (x)) +#define S5PC_ADDR_BASE (0xe0000000) + +#define S5PC_ADDR(x) (S5PC_ADDR_BASE + (x)) -#define S5C_PA_SYS S5C_ADDR(0x00000000) /* Chip ID/OM */ +#define S5PC_PA_ID S5PC_ADDR(0x00000000) /* ID Base */ +#define S5PC_PA_CLK S5PC_ADDR(0x00100000) /* Clock Base */ +#define S5PC_PA_CLK_OTHERS S5PC_ADDR(0x00200000) /* Clock Others Base */ +#define S5PC_PA_GPIO S5PC_ADDR(0x00300000) /* GPIO Base */ +#define S5PC_PA_VIC0 S5PC_ADDR(0x04000000) /* Interrupt Controller 0 */ +#define S5PC_PA_VIC1 S5PC_ADDR(0x04100000) /* Interrupt Controller 1 */ +#define S5PC_PA_VIC2 S5PC_ADDR(0x04200000) /* Interrupt Controller 3 */ +#define S5PC_PA_SROM S5PC_ADDR(0x07000000) /* SROM */ +#define S5PC_PA_ONENAND S5PC_ADDR(0x07100000) /* ONENAND */ +#define S5PC_PA_NAND S5PC_ADDR(0x07200000) /* NAND */ +#define S5PC_PA_PWMTIMER S5PC_ADDR(0x0a000000) /* PWM Timer */ +#define S5PC_PA_WATCHDOG S5PC_ADDR(0x0a200000) /* Watchdog Timer */ +#define S5PC_PA_SYSTEM S5PC_ADDR(0x0a100000) /* System Timer */ +#define S5PC_PA_RTC S5PC_ADDR(0x0a300000) /* RTC */ +#define S5PC_PA_UART S5PC_ADDR(0x0c000000) /* Uart Base */ -#define S5C_PA_VIC S5C_ADDR(0x04000000) /* Interrupt Controller 1 */ -#define S5C_PA_VIC0 S5C_ADDR(0x04000000) /* Interrupt Controller 1 */ -#define S5C_PA_VIC1 S5C_ADDR(0x04100000) /* Interrupt Controller 2 */ -#define S5C_PA_VIC2 S5C_ADDR(0x04200000) /* Interrupt Controller 3 */ +/* Chip ID */ +#define S5PC_ID(x) (S5P_PA_ID + (x)) -#define S5C_PA_MEM S5C_ADDR(0x07000000) /* SROM */ -#define S5C_PA_SROM S5C_ADDR(0x07000000) /* SROM */ -#define S5C_PA_ONENAND S5C_ADDR(0x07100000) /* ONENAND */ -#define S5C_PA_NAND S5C_ADDR(0x07200000) /* NAND */ +#define S5PC_PRO_ID S5PC_ID(0) +#define S5PC_OMR S5PC_ID(4) -#define S5C_PA_TIMER S5C_ADDR(0x0a000000) /* PWM Timer */ -#define S5C_PA_PWMTIMER S5C_ADDR(0x0a000000) /* PWM Timer */ -#define S5C_PA_SYSTEM S5C_ADDR(0x0a100000) /* System Timer */ -#define S5C_PA_WATCHDOG S5C_ADDR(0x0a200000) /* Watchdog Timer */ -#define S5C_PA_RTC S5C_ADDR(0x0a300000) /* RTC */ +/* Clock control */ +#define S5PC_CLKREG(x) (S5P_PA_CLK + (x)) -#define S5C_PA_UART S5C_ADDR(0x0c000000) /* UART */ +#define S5PC_APLL_LOCK S5PC_CLKREG(0x0) +#define S5PC_MPLL_LOCK S5PC_CLKREG(0x4) +#define S5PC_EPLL_LOCK S5PC_CLKREG(0x8) +#define S5PC_HPLL_LOCK S5PC_CLKREG(0xc) +#define S5PC_APLL_CON S5PC_CLKREG(0x100) +#define S5PC_MPLL_CON S5PC_CLKREG(0x104) +#define S5PC_EPLL_CON S5PC_CLKREG(0x108) +#define S5PC_HPLL_CON S5PC_CLKREG(0x10c) + +#define S5PC_CLK_SRC0 S5PC_CLKREG(0x200) +#define S5PC_CLK_SRC1 S5PC_CLKREG(0x204) +#define S5PC_CLK_SRC2 S5PC_CLKREG(0x208) +#define S5PC_CLK_SRC3 S5PC_CLKREG(0x20c) + +#define S5PC_CLK_DIV0 S5PC_CLKREG(0x300) +#define S5PC_CLK_DIV1 S5PC_CLKREG(0x304) +#define S5PC_CLK_DIV2 S5PC_CLKREG(0x308) +#define S5PC_CLK_DIV3 S5PC_CLKREG(0x30c) +#define S5PC_CLK_DIV0 S5PC_CLKREG(0x300) +#define S5PC_CLK_OUT S5PC_CLKREG(0x400) + +#define S5PC_CLK_GATE_D00 S5PC_CLKREG(0x500) +#define S5PC_CLK_GATE_D01 S5PC_CLKREG(0x504) +#define S5PC_CLK_GATE_D02 S5PC_CLKREG(0x508) + +#define S5PC_CLK_GATE_D10 S5PC_CLKREG(0x520) +#define S5PC_CLK_GATE_D11 S5PC_CLKREG(0x524) +#define S5PC_CLK_GATE_D12 S5PC_CLKREG(0x528) +#define S5PC_CLK_GATE_D13 S5PC_CLKREG(0x530) +#define S5PC_CLK_GATE_D14 S5PC_CLKREG(0x534) + +#define S5PC_CLK_GATE_D20 S5PC_CLKREG(0x540) + +#define S5PC_CLK_GATE_SCLK0 S5PC_CLKREG(0x560) +#define S5PC_CLK_GATE_SCLK1 S5PC_CLKREG(0x564) + + +/* Clock control - Others */ +#define S5PC_OTHERS_REG(x) (S5P_PA_CLK_OTHERS + (x)) + +#define S5PC_SW_RST S5PC_OTHERS_REG(0x0) +#define S5PC_ONENAND_RST S5PC_OTHERS_REG(0x8) + +#define S5PC_GENERAL_CTRL S5PC_OTHERS_REG(0x100) +#define S5PC_GENERAL_STATUS S5PC_OTHERS_REG(0x104) + +#define S5PC_MEM_SYS_CFG S5PC_OTHERS_REG(0x200) + +#define S5PC_CAM_MUX_SEL S5PC_OTHERS_REG(0x300) +#define S5PC_MIXER_OUT_SEL S5PC_OTHERS_REG(0x304) +#define S5PC_LPMP3_MODE_SEL S5PC_OTHERS_REG(0x308) + +#define S5PC_MIPI_PHY_CON0 S5PC_OTHERS_REG(0x400) +#define S5PC_MIPI_PHY_CON1 S5PC_OTHERS_REG(0x414) +#define S5PC_HDMI_PHY_CON0 S5PC_OTHERS_REG(0x420) + + +/* GPIO Bank Base */ +#define S5PC_GPIO_BASE(x) (S5PC_PA_GPIO + (x)) + +#define S5PC_GPIO_A_REG(x) (S5PC_GPIO_BASE(0x0) + (x)) +#define S5PC_GPIO_B_REG(x) (S5PC_GPIO_BASE(0x40) + (x)) +#define S5PC_GPIO_C_REG(x) (S5PC_GPIO_BASE(0x60) + (x)) +#define S5PC_GPIO_D_REG(x) (S5PC_GPIO_BASE(0x80) + (x)) +#define S5PC_GPIO_E_REG(x) (S5PC_GPIO_BASE(0xa0) + (x)) +#define S5PC_GPIO_F_REG(x) (S5PC_GPIO_BASE(0xe0) + (x)) +#define S5PC_GPIO_G_REG(x) (S5PC_GPIO_BASE(0x160) + (x)) +#define S5PC_GPIO_I_REG(x) (S5PC_GPIO_BASE(0x1e0) + (x)) +#define S5PC_GPIO_J_REG(x) (S5PC_GPIO_BASE(0x200) + (x)) +#define S5PC_GPIO_K_REG(x) (S5PC_GPIO_BASE(0x2a0) + (x)) +#define S5PC_GPIO_L_REG(x) (S5PC_GPIO_BASE(0x320) + (x)) + +#define S5PC_MP_REG(x) (S5PC_GPIO_BASE(0x3c0) + (x)) +#define S5PC_ETC_REG(x) (S5PC_GPIO_BASE(0x4e0) + (x)) + +#define S5PC_GPIO_INT_CON_REG(x) (S5PC_GPIO_BASE(0x700) + (x)) +#define S5PC_GPIO_INT_FLTCON_REG(x) (S5PC_GPIO_BASE(0x800) + (x)) +#define S5PC_GPIO_INT_MASK_REG(x) (S5PC_GPIO_BASE(0x900) + (x)) +#define S5PC_GPIO_INT_PEND_REG(x) (S5PC_GPIO_BASE(0xa00) + (x)) +#define S5PC_GPIO_INT_PRIO_REG(x) (S5PC_GPIO_BASE(0xb00) + (x)) + +#define S5PC_GPIO_H_REG(x) (S5PC_GPIO_BASE(0xc00) + (x)) + +#define S5PC_WAKEUP_INT_CON(x) (S5PC_GPIO_BASE(0xe00) + (x)) +#define S5PC_WAKEUP_FLTINT_CON(x) (S5PC_GPIO_BASE(0xe80) + (x)) +#define S5PC_WAKEUP_INT_MASK(x) (S5PC_GPIO_BASE(0xf00) + (x)) +#define S5PC_WAKEUP_INT_PEND(x) (S5PC_GPIO_BASE(0xf40) + (x)) + + +/* GPIO Offset */ +#define CON_OFFSET 0x0 +#define DAT_OFFSET 0x4 +#define PULL_OFFSET 0x8 +#define DRV_OFFSET 0xc +#define PDNCON_OFFSET 0x10 +#define PDNPULL_OFFSET 0x14 + + +/* GPIO A Bank Base */ +#define S5PC_GPIO_A0_BASE(x) (S5PC_GPIO_A_REG(0x0) + (x)) +#define S5PC_GPIO_A1_BASE(x) (S5PC_GPIO_A_REG(0x20) + (x)) + +#define S5PC_GPIO_A0_CON S5PC_GPIO_A0_BASE(CON_OFFSET) +#define S5PC_GPIO_A0_DAT S5PC_GPIO_A0_BASE(DAT_OFFSET) +#define S5PC_GPIO_A0_PULL S5PC_GPIO_A0_BASE(PULL_OFFSET) +#define S5PC_GPIO_A0_DRV S5PC_GPIO_A0_BASE(DRV_OFFSET) +#define S5PC_GPIO_A0_PDNCON S5PC_GPIO_A0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_A0_PDNPUL S5PC_GPIO_A0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_A1_CON S5PC_GPIO_A1_BASE(CON_OFFSET) +#define S5PC_GPIO_A1_DAT S5PC_GPIO_A1_BASE(DAT_OFFSET) +#define S5PC_GPIO_A1_PULL S5PC_GPIO_A1_BASE(PULL_OFFSET) +#define S5PC_GPIO_A1_DRV S5PC_GPIO_A1_BASE(DRV_OFFSET) +#define S5PC_GPIO_A1_PDNCON S5PC_GPIO_A1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_A1_PDNPUL S5PC_GPIO_A1_BASE(PDNPULL_OFFSET) + +/* GPIO B Bank Base */ +#define S5PC_GPIO_B_BASE(x) (S5PC_GPIO_B_REG(0x0) + (x)) + +#define S5PC_GPIO_B_CON S5PC_GPIO_B_BASE(CON_OFFSET) +#define S5PC_GPIO_B_DAT S5PC_GPIO_B_BASE(DAT_OFFSET) +#define S5PC_GPIO_B_PULL S5PC_GPIO_B_BASE(PULL_OFFSET) +#define S5PC_GPIO_B_DRV S5PC_GPIO_B_BASE(DRV_OFFSET) +#define S5PC_GPIO_B_PDNCON S5PC_GPIO_B_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_B_PDNPUL S5PC_GPIO_B_BASE(PDNPULL_OFFSET) + +/* GPIO C Bank Base */ +#define S5PC_GPIO_C_BASE(x) (S5PC_GPIO_C_REG(0x0) + (x)) + +#define S5PC_GPIO_C_CON S5PC_GPIO_C_BASE(CON_OFFSET) +#define S5PC_GPIO_C_DAT S5PC_GPIO_C_BASE(DAT_OFFSET) +#define S5PC_GPIO_C_PULL S5PC_GPIO_C_BASE(PULL_OFFSET) +#define S5PC_GPIO_C_DRV S5PC_GPIO_C_BASE(DRV_OFFSET) +#define S5PC_GPIO_C_PDNCON S5PC_GPIO_C_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_C_PDNPUL S5PC_GPIO_C_BASE(PDNPULL_OFFSET) + +/* GPIO D Bank Base */ +#define S5PC_GPIO_D_BASE(x) (S5PC_GPIO_C_REG(0x0) + (x)) + +#define S5PC_GPIO_D_CON S5PC_GPIO_C_BASE(CON_OFFSET) +#define S5PC_GPIO_D_DAT S5PC_GPIO_C_BASE(DAT_OFFSET) +#define S5PC_GPIO_D_PULL S5PC_GPIO_C_BASE(PULL_OFFSET) +#define S5PC_GPIO_D_DRV S5PC_GPIO_C_BASE(DRV_OFFSET) +#define S5PC_GPIO_D_PDNCON S5PC_GPIO_C_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_D_PDNPUL S5PC_GPIO_C_BASE(PDNPULL_OFFSET) + +/* GPIO E Bank Base */ +#define S5PC_GPIO_E0_BASE(x) (S5PC_GPIO_E_REG(0x0) + (x)) +#define S5PC_GPIO_E1_BASE(x) (S5PC_GPIO_E_REG(0x20) + (x)) + +#define S5PC_GPIO_E0_CON S5PC_GPIO_E0_BASE(CON_OFFSET) +#define S5PC_GPIO_E0_DAT S5PC_GPIO_E0_BASE(DAT_OFFSET) +#define S5PC_GPIO_E0_PULL S5PC_GPIO_E0_BASE(PULL_OFFSET) +#define S5PC_GPIO_E0_DRV S5PC_GPIO_E0_BASE(DRV_OFFSET) +#define S5PC_GPIO_E0_PDNCON S5PC_GPIO_E0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_E0_PDNPUL S5PC_GPIO_E0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_E1_CON S5PC_GPIO_E1_BASE(CON_OFFSET) +#define S5PC_GPIO_E1_DAT S5PC_GPIO_E1_BASE(DAT_OFFSET) +#define S5PC_GPIO_E1_PULL S5PC_GPIO_E1_BASE(PULL_OFFSET) +#define S5PC_GPIO_E1_DRV S5PC_GPIO_E1_BASE(DRV_OFFSET) +#define S5PC_GPIO_E1_PDNCON S5PC_GPIO_E1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_E1_PDNPUL S5PC_GPIO_E1_BASE(PDNPULL_OFFSET) + +/* GPIO F Bank Base */ +#define S5PC_GPIO_F0_BASE(x) (S5PC_GPIO_F_REG(0x0) + (x)) +#define S5PC_GPIO_F1_BASE(x) (S5PC_GPIO_F_REG(0x20) + (x)) +#define S5PC_GPIO_F2_BASE(x) (S5PC_GPIO_F_REG(0x40) + (x)) +#define S5PC_GPIO_F3_BASE(x) (S5PC_GPIO_F_REG(0x60) + (x)) + +#define S5PC_GPIO_F0_CON S5PC_GPIO_F0_BASE(CON_OFFSET) +#define S5PC_GPIO_F0_DAT S5PC_GPIO_F0_BASE(DAT_OFFSET) +#define S5PC_GPIO_F0_PULL S5PC_GPIO_F0_BASE(PULL_OFFSET) +#define S5PC_GPIO_F0_DRV S5PC_GPIO_F0_BASE(DRV_OFFSET) +#define S5PC_GPIO_F0_PDNCON S5PC_GPIO_F0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_F0_PDNPUL S5PC_GPIO_F0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_F1_CON S5PC_GPIO_F1_BASE(CON_OFFSET) +#define S5PC_GPIO_F1_DAT S5PC_GPIO_F1_BASE(DAT_OFFSET) +#define S5PC_GPIO_F1_PULL S5PC_GPIO_F1_BASE(PULL_OFFSET) +#define S5PC_GPIO_F1_DRV S5PC_GPIO_F1_BASE(DRV_OFFSET) +#define S5PC_GPIO_F1_PDNCON S5PC_GPIO_F1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_F1_PDNPUL S5PC_GPIO_F1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_F2_CON S5PC_GPIO_F2_BASE(CON_OFFSET) +#define S5PC_GPIO_F2_DAT S5PC_GPIO_F2_BASE(DAT_OFFSET) +#define S5PC_GPIO_F2_PULL S5PC_GPIO_F2_BASE(PULL_OFFSET) +#define S5PC_GPIO_F2_DRV S5PC_GPIO_F2_BASE(DRV_OFFSET) +#define S5PC_GPIO_F2_PDNCON S5PC_GPIO_F2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_F2_PDNPUL S5PC_GPIO_F2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_F3_CON S5PC_GPIO_F3_BASE(CON_OFFSET) +#define S5PC_GPIO_F3_DAT S5PC_GPIO_F3_BASE(DAT_OFFSET) +#define S5PC_GPIO_F3_PULL S5PC_GPIO_F3_BASE(PULL_OFFSET) +#define S5PC_GPIO_F3_DRV S5PC_GPIO_F3_BASE(DRV_OFFSET) +#define S5PC_GPIO_F3_PDNCON S5PC_GPIO_F3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_F3_PDNPUL S5PC_GPIO_F3_BASE(PDNPULL_OFFSET) + +/* GPIO G Bank Base */ +#define S5PC_GPIO_G0_BASE(x) (S5PC_GPIO_G_REG(0x0) + (x)) +#define S5PC_GPIO_G1_BASE(x) (S5PC_GPIO_G_REG(0x20) + (x)) +#define S5PC_GPIO_G2_BASE(x) (S5PC_GPIO_G_REG(0x40) + (x)) +#define S5PC_GPIO_G3_BASE(x) (S5PC_GPIO_G_REG(0x60) + (x)) + +#define S5PC_GPIO_G0_CON S5PC_GPIO_G0_BASE(CON_OFFSET) +#define S5PC_GPIO_G0_DAT S5PC_GPIO_G0_BASE(DAT_OFFSET) +#define S5PC_GPIO_G0_PULL S5PC_GPIO_G0_BASE(PULL_OFFSET) +#define S5PC_GPIO_G0_DRV S5PC_GPIO_G0_BASE(DRV_OFFSET) +#define S5PC_GPIO_G0_PDNCON S5PC_GPIO_G0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_G0_PDNPUL S5PC_GPIO_G0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_G1_CON S5PC_GPIO_G1_BASE(CON_OFFSET) +#define S5PC_GPIO_G1_DAT S5PC_GPIO_G1_BASE(DAT_OFFSET) +#define S5PC_GPIO_G1_PULL S5PC_GPIO_G1_BASE(PULL_OFFSET) +#define S5PC_GPIO_G1_DRV S5PC_GPIO_G1_BASE(DRV_OFFSET) +#define S5PC_GPIO_G1_PDNCON S5PC_GPIO_G1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_G1_PDNPUL S5PC_GPIO_G1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_G2_CON S5PC_GPIO_G2_BASE(CON_OFFSET) +#define S5PC_GPIO_G2_DAT S5PC_GPIO_G2_BASE(DAT_OFFSET) +#define S5PC_GPIO_G2_PULL S5PC_GPIO_G2_BASE(PULL_OFFSET) +#define S5PC_GPIO_G2_DRV S5PC_GPIO_G2_BASE(DRV_OFFSET) +#define S5PC_GPIO_G2_PDNCON S5PC_GPIO_G2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_G2_PDNPUL S5PC_GPIO_G2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_G3_CON S5PC_GPIO_G3_BASE(CON_OFFSET) +#define S5PC_GPIO_G3_DAT S5PC_GPIO_G3_BASE(DAT_OFFSET) +#define S5PC_GPIO_G3_PULL S5PC_GPIO_G3_BASE(PULL_OFFSET) +#define S5PC_GPIO_G3_DRV S5PC_GPIO_G3_BASE(DRV_OFFSET) +#define S5PC_GPIO_G3_PDNCON S5PC_GPIO_G3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_G3_PDNPUL S5PC_GPIO_G3_BASE(PDNPULL_OFFSET) + +/* GPIO I Bank Base */ +#define S5PC_GPIO_I_BASE(x) (S5PC_GPIO_I_REG(0x0) + (x)) + +#define S5PC_GPIO_I_CON S5PC_GPIO_I_BASE(CON_OFFSET) +#define S5PC_GPIO_I_DAT S5PC_GPIO_I_BASE(DAT_OFFSET) +#define S5PC_GPIO_I_PULL S5PC_GPIO_I_BASE(PULL_OFFSET) +#define S5PC_GPIO_I_DRV S5PC_GPIO_I_BASE(DRV_OFFSET) +#define S5PC_GPIO_I_PDNCON S5PC_GPIO_I_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_I_PDNPUL S5PC_GPIO_I_BASE(PDNPULL_OFFSET) + +/* GPIO J Bank Base */ +#define S5PC_GPIO_J0_BASE(x) (S5PC_GPIO_J_REG(0x0) + (x)) +#define S5PC_GPIO_J1_BASE(x) (S5PC_GPIO_J_REG(0x20) + (x)) +#define S5PC_GPIO_J2_BASE(x) (S5PC_GPIO_J_REG(0x40) + (x)) +#define S5PC_GPIO_J3_BASE(x) (S5PC_GPIO_J_REG(0x60) + (x)) +#define S5PC_GPIO_J4_BASE(x) (S5PC_GPIO_J_REG(0x80) + (x)) + +#define S5PC_GPIO_J0_CON S5PC_GPIO_J0_BASE(CON_OFFSET) +#define S5PC_GPIO_J0_DAT S5PC_GPIO_J0_BASE(DAT_OFFSET) +#define S5PC_GPIO_J0_PULL S5PC_GPIO_J0_BASE(PULL_OFFSET) +#define S5PC_GPIO_J0_DRV S5PC_GPIO_J0_BASE(DRV_OFFSET) +#define S5PC_GPIO_J0_PDNCON S5PC_GPIO_J0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_J0_PDNPUL S5PC_GPIO_J0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_J1_CON S5PC_GPIO_J1_BASE(CON_OFFSET) +#define S5PC_GPIO_J1_DAT S5PC_GPIO_J1_BASE(DAT_OFFSET) +#define S5PC_GPIO_J1_PULL S5PC_GPIO_J1_BASE(PULL_OFFSET) +#define S5PC_GPIO_J1_DRV S5PC_GPIO_J1_BASE(DRV_OFFSET) +#define S5PC_GPIO_J1_PDNCON S5PC_GPIO_J1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_J1_PDNPUL S5PC_GPIO_J1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_J2_CON S5PC_GPIO_J2_BASE(CON_OFFSET) +#define S5PC_GPIO_J2_DAT S5PC_GPIO_J2_BASE(DAT_OFFSET) +#define S5PC_GPIO_J2_PULL S5PC_GPIO_J2_BASE(PULL_OFFSET) +#define S5PC_GPIO_J2_DRV S5PC_GPIO_J2_BASE(DRV_OFFSET) +#define S5PC_GPIO_J2_PDNCON S5PC_GPIO_J2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_J2_PDNPUL S5PC_GPIO_J2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_J3_CON S5PC_GPIO_J3_BASE(CON_OFFSET) +#define S5PC_GPIO_J3_DAT S5PC_GPIO_J3_BASE(DAT_OFFSET) +#define S5PC_GPIO_J3_PULL S5PC_GPIO_J3_BASE(PULL_OFFSET) +#define S5PC_GPIO_J3_DRV S5PC_GPIO_J3_BASE(DRV_OFFSET) +#define S5PC_GPIO_J3_PDNCON S5PC_GPIO_J3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_J3_PDNPUL S5PC_GPIO_J3_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_J4_CON S5PC_GPIO_J4_BASE(CON_OFFSET) +#define S5PC_GPIO_J4_DAT S5PC_GPIO_J4_BASE(DAT_OFFSET) +#define S5PC_GPIO_J4_PULL S5PC_GPIO_J4_BASE(PULL_OFFSET) +#define S5PC_GPIO_J4_DRV S5PC_GPIO_J4_BASE(DRV_OFFSET) +#define S5PC_GPIO_J4_PDNCON S5PC_GPIO_J4_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_J4_PDNPUL S5PC_GPIO_J4_BASE(PDNPULL_OFFSET) + +/* GPIO K Bank Base */ +#define S5PC_GPIO_K0_BASE(x) (S5PC_GPIO_K_REG(0x0) + (x)) +#define S5PC_GPIO_K1_BASE(x) (S5PC_GPIO_K_REG(0x20) + (x)) +#define S5PC_GPIO_K2_BASE(x) (S5PC_GPIO_K_REG(0x40) + (x)) +#define S5PC_GPIO_K3_BASE(x) (S5PC_GPIO_K_REG(0x60) + (x)) + +#define S5PC_GPIO_K0_CON S5PC_GPIO_K0_BASE(CON_OFFSET) +#define S5PC_GPIO_K0_DAT S5PC_GPIO_K0_BASE(DAT_OFFSET) +#define S5PC_GPIO_K0_PULL S5PC_GPIO_K0_BASE(PULL_OFFSET) +#define S5PC_GPIO_K0_DRV S5PC_GPIO_K0_BASE(DRV_OFFSET) +#define S5PC_GPIO_K0_PDNCON S5PC_GPIO_K0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_K0_PDNPUL S5PC_GPIO_K0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_K1_CON S5PC_GPIO_K1_BASE(CON_OFFSET) +#define S5PC_GPIO_K1_DAT S5PC_GPIO_K1_BASE(DAT_OFFSET) +#define S5PC_GPIO_K1_PULL S5PC_GPIO_K1_BASE(PULL_OFFSET) +#define S5PC_GPIO_K1_DRV S5PC_GPIO_K1_BASE(DRV_OFFSET) +#define S5PC_GPIO_K1_PDNCON S5PC_GPIO_K1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_K1_PDNPUL S5PC_GPIO_K1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_K2_CON S5PC_GPIO_K2_BASE(CON_OFFSET) +#define S5PC_GPIO_K2_DAT S5PC_GPIO_K2_BASE(DAT_OFFSET) +#define S5PC_GPIO_K2_PULL S5PC_GPIO_K2_BASE(PULL_OFFSET) +#define S5PC_GPIO_K2_DRV S5PC_GPIO_K2_BASE(DRV_OFFSET) +#define S5PC_GPIO_K2_PDNCON S5PC_GPIO_K2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_K2_PDNPUL S5PC_GPIO_K2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_K3_CON S5PC_GPIO_K3_BASE(CON_OFFSET) +#define S5PC_GPIO_K3_DAT S5PC_GPIO_K3_BASE(DAT_OFFSET) +#define S5PC_GPIO_K3_PULL S5PC_GPIO_K3_BASE(PULL_OFFSET) +#define S5PC_GPIO_K3_DRV S5PC_GPIO_K3_BASE(DRV_OFFSET) +#define S5PC_GPIO_K3_PDNCON S5PC_GPIO_K3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_K3_PDNPUL S5PC_GPIO_K3_BASE(PDNPULL_OFFSET) + +/* GPIO L Bank */ +#define S5PC_GPIO_L0_BASE(x) (S5PC_GPIO_L_REG(0x0) + (x)) +#define S5PC_GPIO_L1_BASE(x) (S5PC_GPIO_L_REG(0x20) + (x)) +#define S5PC_GPIO_L2_BASE(x) (S5PC_GPIO_L_REG(0x40) + (x)) +#define S5PC_GPIO_L3_BASE(x) (S5PC_GPIO_L_REG(0x60) + (x)) +#define S5PC_GPIO_L4_BASE(x) (S5PC_GPIO_L_REG(0x80) + (x)) + +#define S5PC_GPIO_L0_CON S5PC_GPIO_L0_BASE(CON_OFFSET) +#define S5PC_GPIO_L0_DAT S5PC_GPIO_L0_BASE(DAT_OFFSET) +#define S5PC_GPIO_L0_PULL S5PC_GPIO_L0_BASE(PULL_OFFSET) +#define S5PC_GPIO_L0_DRV S5PC_GPIO_L0_BASE(DRV_OFFSET) +#define S5PC_GPIO_L0_PDNCON S5PC_GPIO_L0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_L0_PDNPUL S5PC_GPIO_L0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_L1_CON S5PC_GPIO_L1_BASE(CON_OFFSET) +#define S5PC_GPIO_L1_DAT S5PC_GPIO_L1_BASE(DAT_OFFSET) +#define S5PC_GPIO_L1_PULL S5PC_GPIO_L1_BASE(PULL_OFFSET) +#define S5PC_GPIO_L1_DRV S5PC_GPIO_L1_BASE(DRV_OFFSET) +#define S5PC_GPIO_L1_PDNCON S5PC_GPIO_L1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_L1_PDNPUL S5PC_GPIO_L1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_L2_CON S5PC_GPIO_L2_BASE(CON_OFFSET) +#define S5PC_GPIO_L2_DAT S5PC_GPIO_L2_BASE(DAT_OFFSET) +#define S5PC_GPIO_L2_PULL S5PC_GPIO_L2_BASE(PULL_OFFSET) +#define S5PC_GPIO_L2_DRV S5PC_GPIO_L2_BASE(DRV_OFFSET) +#define S5PC_GPIO_L2_PDNCON S5PC_GPIO_L2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_L2_PDNPUL S5PC_GPIO_L2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_L3_CON S5PC_GPIO_L3_BASE(CON_OFFSET) +#define S5PC_GPIO_L3_DAT S5PC_GPIO_L3_BASE(DAT_OFFSET) +#define S5PC_GPIO_L3_PULL S5PC_GPIO_L3_BASE(PULL_OFFSET) +#define S5PC_GPIO_L3_DRV S5PC_GPIO_L3_BASE(DRV_OFFSET) +#define S5PC_GPIO_L3_PDNCON S5PC_GPIO_L3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_L3_PDNPUL S5PC_GPIO_L3_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_L4_CON S5PC_GPIO_L4_BASE(CON_OFFSET) +#define S5PC_GPIO_L4_DAT S5PC_GPIO_L4_BASE(DAT_OFFSET) +#define S5PC_GPIO_L4_PULL S5PC_GPIO_L4_BASE(PULL_OFFSET) +#define S5PC_GPIO_L4_DRV S5PC_GPIO_L4_BASE(DRV_OFFSET) +#define S5PC_GPIO_L4_PDNCON S5PC_GPIO_L4_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_L4_PDNPUL S5PC_GPIO_L4_BASE(PDNPULL_OFFSET) + +/* GPIO MP Bank */ +#define S5PC_MP_0_BASE(x) (S5PC_MP_REG(0x0) + (x)) +#define S5PC_MP_1_BASE(x) (S5PC_MP_REG(0x20) + (x)) +#define S5PC_MP_2_BASE(x) (S5PC_MP_REG(0x40) + (x)) +#define S5PC_MP_3_BASE(x) (S5PC_MP_REG(0x60) + (x)) +#define S5PC_MP_4_BASE(x) (S5PC_MP_REG(0x80) + (x)) +#define S5PC_MP_5_BASE(x) (S5PC_MP_REG(0xa0) + (x)) +#define S5PC_MP_6_BASE(x) (S5PC_MP_REG(0xc0) + (x)) +#define S5PC_MP_7_BASE(x) (S5PC_MP_REG(0xe0) + (x)) + +#define S5PC_MP_0PULL S5PC_MP_0_BASE(PULL_OFFSET) +#define S5PC_MP_0DRV S5PC_MP_0_BASE(DRV_OFFSET) +#define S5PC_MP_0PDNPULL S5PC_MP_0_BASE(PDNPULL_OFFSET) + +#define S5PC_MP_1PULL S5PC_MP_1_BASE(PULL_OFFSET) +#define S5PC_MP_1DRV S5PC_MP_1_BASE(DRV_OFFSET) +#define S5PC_MP_1PDNPULL S5PC_MP_1_BASE(PDNPULL_OFFSET) + +#define S5PC_MP_2PULL S5PC_MP_2_BASE(PULL_OFFSET) +#define S5PC_MP_2DRV S5PC_MP_2_BASE(DRV_OFFSET) +#define S5PC_MP_2PDNPULL S5PC_MP_2_BASE(PDNPULL_OFFSET) + +#define S5PC_MP_3DRV S5PC_MP_3_BASE(DRV_OFFSET) +#define S5PC_MP_4DRV S5PC_MP_4_BASE(DRV_OFFSET) +#define S5PC_MP_5DRV S5PC_MP_5_BASE(DRV_OFFSET) +#define S5PC_MP_6DRV S5PC_MP_6_BASE(DRV_OFFSET) +#define S5PC_MP_7DRV S5PC_MP_7_BASE(DRV_OFFSET) +#define S5PC_MP_8DRV S5PC_MP_8_BASE(DRV_OFFSET) + +/* GPIO ETC Bank */ +#define S5PC_ETC0_BASE(x) (S5PC_ETC_REG(0x0) + (x)) +#define S5PC_ETC1_BASE(x) (S5PC_ETC_REG(0x20) + (x)) +#define S5PC_ETC2_BASE(x) (S5PC_ETC_REG(0x40) + (x)) +#define S5PC_ETC3_BASE(x) (S5PC_ETC_REG(0x60) + (x)) +#define S5PC_ETC4_BASE(x) (S5PC_ETC_REG(0x80) + (x)) + +#define S5PC_ETC0PULL S5PC_ETC0_BASE(PULL_OFFSET) +#define S5PC_ETC0DRV S5PC_ETC0_BASE(DRV_OFFSET) +#define S5PC_ETC1PULL S5PC_ETC1_BASE(PULL_OFFSET) +#define S5PC_ETC1DRV S5PC_ETC1_BASE(DRV_OFFSET) +#define S5PC_ETC2PULL S5PC_ETC2_BASE(PULL_OFFSET) +#define S5PC_ETC2DRV S5PC_ETC2_BASE(DRV_OFFSET) +#define S5PC_ETC3PULL S5PC_ETC3_BASE(PULL_OFFSET) +#define S5PC_ETC3DRV S5PC_ETC3_BASE(DRV_OFFSET) +#define S5PC_ETC4DRV S5PC_ETC4_BASE(DRV_OFFSET) + +/* GPIO External Interrupt */ +#define S5PC_GPIO_INT0_CON S5PC_GPIO_INT_CON_REG(0x0) +#define S5PC_GPIO_INT1_CON S5PC_GPIO_INT_CON_REG(0x4) +#define S5PC_GPIO_INT2_CON S5PC_GPIO_INT_CON_REG(0x8) +#define S5PC_GPIO_INT3_CON S5PC_GPIO_INT_CON_REG(0xc) +#define S5PC_GPIO_INT4_CON S5PC_GPIO_INT_CON_REG(0x10) +#define S5PC_GPIO_INT5_CON S5PC_GPIO_INT_CON_REG(0x14) +#define S5PC_GPIO_INT6_CON S5PC_GPIO_INT_CON_REG(0x18) +#define S5PC_GPIO_INT7_CON S5PC_GPIO_INT_CON_REG(0x1c) +#define S5PC_GPIO_INT8_CON S5PC_GPIO_INT_CON_REG(0x20) +#define S5PC_GPIO_INT9_CON S5PC_GPIO_INT_CON_REG(0x24) +#define S5PC_GPIO_INT10_CON S5PC_GPIO_INT_CON_REG(0x28) +#define S5PC_GPIO_INT11_CON S5PC_GPIO_INT_CON_REG(0x2c) +#define S5PC_GPIO_INT12_CON S5PC_GPIO_INT_CON_REG(0x30) +#define S5PC_GPIO_INT13_CON S5PC_GPIO_INT_CON_REG(0x34) +#define S5PC_GPIO_INT14_CON S5PC_GPIO_INT_CON_REG(0x38) +#define S5PC_GPIO_INT15_CON S5PC_GPIO_INT_CON_REG(0x3c) +#define S5PC_GPIO_INT16_CON S5PC_GPIO_INT_CON_REG(0x40) +#define S5PC_GPIO_INT17_CON S5PC_GPIO_INT_CON_REG(0x44) +#define S5PC_GPIO_INT18_CON S5PC_GPIO_INT_CON_REG(0x48) +#define S5PC_GPIO_INT19_CON S5PC_GPIO_INT_CON_REG(0x4c) +#define S5PC_GPIO_INT20_CON S5PC_GPIO_INT_CON_REG(0x50) + +#define S5PC_GPIO_INT0_FLTCON0 S5PC_GPIO_INT_CON_REG(0x0) +#define S5PC_GPIO_INT0_FLTCON1 S5PC_GPIO_INT_CON_REG(0x4) +#define S5PC_GPIO_INT1_FLTCON0 S5PC_GPIO_INT_CON_REG(0x8) +#define S5PC_GPIO_INT1_FLTCON1 S5PC_GPIO_INT_CON_REG(0xc) +#define S5PC_GPIO_INT2_FLTCON0 S5PC_GPIO_INT_CON_REG(0x10) +#define S5PC_GPIO_INT2_FLTCON1 S5PC_GPIO_INT_CON_REG(0x14) +#define S5PC_GPIO_INT3_FLTCON0 S5PC_GPIO_INT_CON_REG(0x18) +#define S5PC_GPIO_INT3_FLTCON1 S5PC_GPIO_INT_CON_REG(0x1c) +#define S5PC_GPIO_INT4_FLTCON0 S5PC_GPIO_INT_CON_REG(0x20) +#define S5PC_GPIO_INT4_FLTCON1 S5PC_GPIO_INT_CON_REG(0x24) +#define S5PC_GPIO_INT5_FLTCON0 S5PC_GPIO_INT_CON_REG(0x28) +#define S5PC_GPIO_INT5_FLTCON1 S5PC_GPIO_INT_CON_REG(0x2c) +#define S5PC_GPIO_INT6_FLTCON0 S5PC_GPIO_INT_CON_REG(0x30) +#define S5PC_GPIO_INT6_FLTCON1 S5PC_GPIO_INT_CON_REG(0x34) +#define S5PC_GPIO_INT7_FLTCON0 S5PC_GPIO_INT_CON_REG(0x38) +#define S5PC_GPIO_INT7_FLTCON1 S5PC_GPIO_INT_CON_REG(0x3c) +#define S5PC_GPIO_INT8_FLTCON0 S5PC_GPIO_INT_CON_REG(0x40) +#define S5PC_GPIO_INT8_FLTCON1 S5PC_GPIO_INT_CON_REG(0x44) +#define S5PC_GPIO_INT9_FLTCON0 S5PC_GPIO_INT_CON_REG(0x48) +#define S5PC_GPIO_INT9_FLTCON1 S5PC_GPIO_INT_CON_REG(0x4c) +#define S5PC_GPIO_INT10_FLTCON0 S5PC_GPIO_INT_CON_REG(0x50) +#define S5PC_GPIO_INT11_FLTCON0 S5PC_GPIO_INT_CON_REG(0x58) +#define S5PC_GPIO_INT11_FLTCON1 S5PC_GPIO_INT_CON_REG(0x5c) +#define S5PC_GPIO_INT12_FLTCON0 S5PC_GPIO_INT_CON_REG(0x60) +#define S5PC_GPIO_INT13_FLTCON0 S5PC_GPIO_INT_CON_REG(0x68) +#define S5PC_GPIO_INT13_FLTCON1 S5PC_GPIO_INT_CON_REG(0x6c) +#define S5PC_GPIO_INT14_FLTCON0 S5PC_GPIO_INT_CON_REG(0x70) +#define S5PC_GPIO_INT14_FLTCON1 S5PC_GPIO_INT_CON_REG(0x74) +#define S5PC_GPIO_INT15_FLTCON0 S5PC_GPIO_INT_CON_REG(0x78) +#define S5PC_GPIO_INT15_FLTCON1 S5PC_GPIO_INT_CON_REG(0x7c) +#define S5PC_GPIO_INT16_FLTCON0 S5PC_GPIO_INT_CON_REG(0x80) +#define S5PC_GPIO_INT16_FLTCON1 S5PC_GPIO_INT_CON_REG(0x84) +#define S5PC_GPIO_INT17_FLTCON0 S5PC_GPIO_INT_CON_REG(0x88) +#define S5PC_GPIO_INT17_FLTCON1 S5PC_GPIO_INT_CON_REG(0x8c) +#define S5PC_GPIO_INT18_FLTCON0 S5PC_GPIO_INT_CON_REG(0x90) +#define S5PC_GPIO_INT18_FLTCON1 S5PC_GPIO_INT_CON_REG(0x94) +#define S5PC_GPIO_INT19_FLTCON0 S5PC_GPIO_INT_CON_REG(0x98) +#define S5PC_GPIO_INT19_FLTCON1 S5PC_GPIO_INT_CON_REG(0x9c) +#define S5PC_GPIO_INT20_FLTCON0 S5PC_GPIO_INT_CON_REG(0xa0) + +#define S5PC_GPIO_INT0_MASK S5PC_GPIO_INT_MASK_REG(0x00) +#define S5PC_GPIO_INT1_MASK S5PC_GPIO_INT_MASK_REG(0x04) +#define S5PC_GPIO_INT2_MASK S5PC_GPIO_INT_MASK_REG(0x08) +#define S5PC_GPIO_INT3_MASK S5PC_GPIO_INT_MASK_REG(0x0c) +#define S5PC_GPIO_INT4_MASK S5PC_GPIO_INT_MASK_REG(0x10) +#define S5PC_GPIO_INT5_MASK S5PC_GPIO_INT_MASK_REG(0x14) +#define S5PC_GPIO_INT6_MASK S5PC_GPIO_INT_MASK_REG(0x18) +#define S5PC_GPIO_INT7_MASK S5PC_GPIO_INT_MASK_REG(0x1c) +#define S5PC_GPIO_INT8_MASK S5PC_GPIO_INT_MASK_REG(0x20) +#define S5PC_GPIO_INT9_MASK S5PC_GPIO_INT_MASK_REG(0x24) +#define S5PC_GPIO_INT10_MASK S5PC_GPIO_INT_MASK_REG(0x28) +#define S5PC_GPIO_INT11_MASK S5PC_GPIO_INT_MASK_REG(0x2c) +#define S5PC_GPIO_INT12_MASK S5PC_GPIO_INT_MASK_REG(0x30) +#define S5PC_GPIO_INT13_MASK S5PC_GPIO_INT_MASK_REG(0x34) +#define S5PC_GPIO_INT14_MASK S5PC_GPIO_INT_MASK_REG(0x38) +#define S5PC_GPIO_INT15_MASK S5PC_GPIO_INT_MASK_REG(0x3c) +#define S5PC_GPIO_INT16_MASK S5PC_GPIO_INT_MASK_REG(0x40) +#define S5PC_GPIO_INT17_MASK S5PC_GPIO_INT_MASK_REG(0x44) +#define S5PC_GPIO_INT18_MASK S5PC_GPIO_INT_MASK_REG(0x48) +#define S5PC_GPIO_INT19_MASK S5PC_GPIO_INT_MASK_REG(0x4c) +#define S5PC_GPIO_INT20_MASK S5PC_GPIO_INT_MASK_REG(0x50) + +#define S5PC_GPIO_INT0_PEND S5PC_GPIO_INT_PEND_REG(0x00) +#define S5PC_GPIO_INT1_PEND S5PC_GPIO_INT_PEND_REG(0x04) +#define S5PC_GPIO_INT2_PEND S5PC_GPIO_INT_PEND_REG(0x08) +#define S5PC_GPIO_INT3_PEND S5PC_GPIO_INT_PEND_REG(0x0c) +#define S5PC_GPIO_INT4_PEND S5PC_GPIO_INT_PEND_REG(0x10) +#define S5PC_GPIO_INT5_PEND S5PC_GPIO_INT_PEND_REG(0x14) +#define S5PC_GPIO_INT6_PEND S5PC_GPIO_INT_PEND_REG(0x18) +#define S5PC_GPIO_INT7_PEND S5PC_GPIO_INT_PEND_REG(0x1c) +#define S5PC_GPIO_INT8_PEND S5PC_GPIO_INT_PEND_REG(0x20) +#define S5PC_GPIO_INT9_PEND S5PC_GPIO_INT_PEND_REG(0x24) +#define S5PC_GPIO_INT10_PEND S5PC_GPIO_INT_PEND_REG(0x28) +#define S5PC_GPIO_INT11_PEND S5PC_GPIO_INT_PEND_REG(0x2c) +#define S5PC_GPIO_INT12_PEND S5PC_GPIO_INT_PEND_REG(0x30) +#define S5PC_GPIO_INT13_PEND S5PC_GPIO_INT_PEND_REG(0x34) +#define S5PC_GPIO_INT14_PEND S5PC_GPIO_INT_PEND_REG(0x38) +#define S5PC_GPIO_INT15_PEND S5PC_GPIO_INT_PEND_REG(0x3c) +#define S5PC_GPIO_INT16_PEND S5PC_GPIO_INT_PEND_REG(0x40) +#define S5PC_GPIO_INT17_PEND S5PC_GPIO_INT_PEND_REG(0x44) +#define S5PC_GPIO_INT18_PEND S5PC_GPIO_INT_PEND_REG(0x48) +#define S5PC_GPIO_INT19_PEND S5PC_GPIO_INT_PEND_REG(0x4c) +#define S5PC_GPIO_INT20_PEND S5PC_GPIO_INT_PEND_REG(0x50) + +#define S5PC_GPIO_INT_GRPPRI S5PC_GPIO_INT_PRIO_REG(0x00) +#define S5PC_GPIO_INT_PRIORITY S5PC_GPIO_INT_PRIO_REG(0x04) +#define S5PC_GPIO_INT_SERVICE S5PC_GPIO_INT_PRIO_REG(0x08) +#define S5PC_GPIO_INT_SERVICE_PEND S5PC_GPIO_INT_PRIO_REG(0x0c) +#define S5PC_GPIO_INT_GRPFIXPRI S5PC_GPIO_INT_PRIO_REG(0x10) + +#define S5PC_GPIO_INT0_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x14) +#define S5PC_GPIO_INT1_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x18) +#define S5PC_GPIO_INT2_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x1c) +#define S5PC_GPIO_INT3_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x20) +#define S5PC_GPIO_INT4_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x24) +#define S5PC_GPIO_INT5_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x28) +#define S5PC_GPIO_INT6_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x2c) +#define S5PC_GPIO_INT7_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x30) +#define S5PC_GPIO_INT8_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x34) +#define S5PC_GPIO_INT9_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x38) +#define S5PC_GPIO_INT10_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x3c) +#define S5PC_GPIO_INT11_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x40) +#define S5PC_GPIO_INT12_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x44) +#define S5PC_GPIO_INT13_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x48) +#define S5PC_GPIO_INT14_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x4c) +#define S5PC_GPIO_INT15_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x50) +#define S5PC_GPIO_INT16_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x54) +#define S5PC_GPIO_INT17_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x58) +#define S5PC_GPIO_INT18_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x5c) +#define S5PC_GPIO_INT19_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x60) +#define S5PC_GPIO_INT20_FIXPRI S5PC_GPIO_INT_PRIO_REG(0x64) + +/* GPIO H Bank Base */ +#define S5PC_GPIO_H0_BASE(x) (S5PC_GPIO_H_REG(0x0) + (x)) +#define S5PC_GPIO_H1_BASE(x) (S5PC_GPIO_H_REG(0x20) + (x)) +#define S5PC_GPIO_H2_BASE(x) (S5PC_GPIO_H_REG(0x40) + (x)) +#define S5PC_GPIO_H3_BASE(x) (S5PC_GPIO_H_REG(0x60) + (x)) + +#define S5PC_GPIO_H0_CON S5PC_GPIO_H0_BASE(CON_OFFSET) +#define S5PC_GPIO_H0_DAT S5PC_GPIO_H0_BASE(DAT_OFFSET) +#define S5PC_GPIO_H0_PULL S5PC_GPIO_H0_BASE(PULL_OFFSET) +#define S5PC_GPIO_H0_DRV S5PC_GPIO_H0_BASE(DRV_OFFSET) +#define S5PC_GPIO_H0_PDNCON S5PC_GPIO_H0_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_H0_PDNPUL S5PC_GPIO_H0_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_H1_CON S5PC_GPIO_H1_BASE(CON_OFFSET) +#define S5PC_GPIO_H1_DAT S5PC_GPIO_H1_BASE(DAT_OFFSET) +#define S5PC_GPIO_H1_PULL S5PC_GPIO_H1_BASE(PULL_OFFSET) +#define S5PC_GPIO_H1_DRV S5PC_GPIO_H1_BASE(DRV_OFFSET) +#define S5PC_GPIO_H1_PDNCON S5PC_GPIO_H1_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_H1_PDNPUL S5PC_GPIO_H1_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_H2_CON S5PC_GPIO_H2_BASE(CON_OFFSET) +#define S5PC_GPIO_H2_DAT S5PC_GPIO_H2_BASE(DAT_OFFSET) +#define S5PC_GPIO_H2_PULL S5PC_GPIO_H2_BASE(PULL_OFFSET) +#define S5PC_GPIO_H2_DRV S5PC_GPIO_H2_BASE(DRV_OFFSET) +#define S5PC_GPIO_H2_PDNCON S5PC_GPIO_H2_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_H2_PDNPUL S5PC_GPIO_H2_BASE(PDNPULL_OFFSET) + +#define S5PC_GPIO_H3_CON S5PC_GPIO_H3_BASE(CON_OFFSET) +#define S5PC_GPIO_H3_DAT S5PC_GPIO_H3_BASE(DAT_OFFSET) +#define S5PC_GPIO_H3_PULL S5PC_GPIO_H3_BASE(PULL_OFFSET) +#define S5PC_GPIO_H3_DRV S5PC_GPIO_H3_BASE(DRV_OFFSET) +#define S5PC_GPIO_H3_PDNCON S5PC_GPIO_H3_BASE(PDNCON_OFFSET) +#define S5PC_GPIO_H3_PDNPUL S5PC_GPIO_H3_BASE(PDNPULL_OFFSET) + +/* GPIO Wakeup Interrupt Configuration */ +#define S5PC_GPIO_WAKEUP_INT0_CON S5PC_WAKEUP_INT_CON(0x00) +#define S5PC_GPIO_WAKEUP_INT1_CON S5PC_WAKEUP_INT_CON(0x04) +#define S5PC_GPIO_WAKEUP_INT2_CON S5PC_WAKEUP_INT_CON(0x08) +#define S5PC_GPIO_WAKEUP_INT3_CON S5PC_WAKEUP_INT_CON(0x0c) + +/* GPIO Wakeup Interrupt Filter Configuration */ +#define S5PC_GPIO_WAKEUP_FLTINT0_CON0 S5PC_WAKEUP_FLTINT_CON(0x00) +#define S5PC_GPIO_WAKEUP_FLTINT0_CON1 S5PC_WAKEUP_FLTINT_CON(0x04) +#define S5PC_GPIO_WAKEUP_FLTINT1_CON0 S5PC_WAKEUP_FLTINT_CON(0x08) +#define S5PC_GPIO_WAKEUP_FLTINT1_CON1 S5PC_WAKEUP_FLTINT_CON(0x0c) +#define S5PC_GPIO_WAKEUP_FLTINT2_CON0 S5PC_WAKEUP_FLTINT_CON(0x10) +#define S5PC_GPIO_WAKEUP_FLTINT2_CON1 S5PC_WAKEUP_FLTINT_CON(0x14) +#define S5PC_GPIO_WAKEUP_FLTINT3_CON0 S5PC_WAKEUP_FLTINT_CON(0x18) +#define S5PC_GPIO_WAKEUP_FLTINT3_CON1 S5PC_WAKEUP_FLTINT_CON(0x1c) + +/* GPIO Wakeup Interrupt Mask */ +#define S5PC_GPIO_WAKEUP_INT0_MASK S5PC_WAKEUP_INT_MASK(0x00) +#define S5PC_GPIO_WAKEUP_INT1_MASK S5PC_WAKEUP_INT_MASK(0x04) +#define S5PC_GPIO_WAKEUP_INT2_MASK S5PC_WAKEUP_INT_MASK(0x08) +#define S5PC_GPIO_WAKEUP_INT3_MASK S5PC_WAKEUP_INT_MASK(0x0c) + +/* GPIO Wakeup Interrupt Pend */ +#define S5PC_GPIO_WAKEUP_INT0_PEND S5PC_WAKEUP_INT_PEND(0x00) +#define S5PC_GPIO_WAKEUP_INT1_PEND S5PC_WAKEUP_INT_PEND(0x04) +#define S5PC_GPIO_WAKEUP_INT2_PEND S5PC_WAKEUP_INT_PEND(0x08) +#define S5PC_GPIO_WAKEUP_INT3_PEND S5PC_WAKEUP_INT_PEND(0x0c) + + + +/* + * Interrupt + * : VIC0, VIC1, VIC2 + */ -#define S3C_IDREG(x) (S3C_PA_SYS + (x)) /* - * Clock Controller + * Memory + * : SROM, Onenand, Nand, SDRAM */ -#define S5C_PA_ID S5C_ADDR(0x00000000) /* Chip ID/OM */ -#define S5C_PA_CLK1 S5C_ADDR(0x00100000) /* Clock Controller 1 */ -#define S5C_PA_CLK2 S5C_ADDR(0x00200000) /* Clock Controller 2 */ -#define S5C_PA_GPIO S5C_ADDR(0x00300000) /* GPIO */ /* - * GPIO + * Timer + * : PWM, Watchdog, System timer, RTC */ -/* GPIO Bank A */ - -/* Bus Matrix */ - -/* Memory controller */ - -/* SDRAM Controller */ - -/* Memory Chip direct command */ - -/* Nand flash controller */ - -/* Interrupt */ -/* Watchdog timer */ -/* UART */ +/* + * UART + */ +#define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */ -/* PWM timer */ -/* Fields */ +#endif /*__S5PC100_H__*/ -/* bits */ -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -/* Memory Parameters */ -/* DDR Parameters */ -/* mDDR memory configuration */ -#endif /*__S5PC100_H__*/