From: Caio Oliveira <caio.oliveira@intel.com>
Date: Sun, 23 Jan 2022 21:08:03 +0000 (-0800)
Subject: intel/fs/xehp: Add unit test for handling of RaR deps across multiple pipelines.
X-Git-Tag: upstream/22.3.5~13489
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=448a840b397556936153a7f82dda4b8ba19d9805;p=platform%2Fupstream%2Fmesa.git

intel/fs/xehp: Add unit test for handling of RaR deps across multiple pipelines.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
---

diff --git a/src/intel/compiler/test_fs_scoreboard.cpp b/src/intel/compiler/test_fs_scoreboard.cpp
index 3be8877..adfa09b 100644
--- a/src/intel/compiler/test_fs_scoreboard.cpp
+++ b/src/intel/compiler/test_fs_scoreboard.cpp
@@ -876,3 +876,32 @@ TEST_F(scoreboard_test, conditional8)
    EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
    EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
 }
+
+TEST_F(scoreboard_test, gfx125_RaR_over_different_pipes)
+{
+   devinfo->verx10 = 125;
+
+   const fs_builder &bld = v->bld;
+
+   fs_reg a = v->vgrf(glsl_type::int_type);
+   fs_reg b = v->vgrf(glsl_type::int_type);
+   fs_reg f = v->vgrf(glsl_type::float_type);
+   fs_reg x = v->vgrf(glsl_type::int_type);
+
+   bld.ADD(f, x, x);
+   bld.ADD(a, x, x);
+   bld.ADD(x, b, b);
+
+   v->calculate_cfg();
+   bblock_t *block0 = v->cfg->blocks[0];
+   ASSERT_EQ(0, block0->start_ip);
+   ASSERT_EQ(2, block0->end_ip);
+
+   lower_scoreboard(v);
+   ASSERT_EQ(0, block0->start_ip);
+   ASSERT_EQ(2, block0->end_ip);
+
+   EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
+   EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
+   EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(1));
+}