From: Amir Ayupov <aaupov@fb.com>
Date: Mon, 13 Jun 2022 21:31:06 +0000 (-0700)
Subject: [BOLT] Use 32-bit MOV to zero 64-bit register in instrumentation code
X-Git-Tag: upstream/15.0.7~4223
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=445bc88501f8f3e55293910dddd6c5fed87b0a0b;p=platform%2Fupstream%2Fllvm.git

[BOLT] Use 32-bit MOV to zero 64-bit register in instrumentation code

Instead of `movabsq $0x0, %rax` emit shorter equivalent `movl $0x0, %eax`.
Intel SDM, 3.4.1.1 General-Purpose Registers in 64-Bit Mode:
>32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in
> the destination general-purpose register.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D127045
---

diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
index 9c45314..413d88d 100644
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -3129,7 +3129,12 @@ public:
     case 1: Opcode = X86::MOV8ri; break;
     case 2: Opcode = X86::MOV16ri; break;
     case 4: Opcode = X86::MOV32ri; break;
-    case 8: Opcode = X86::MOV64ri; break;
+    // Writing to a 32-bit register always zeros the upper 32 bits of the
+    // full-width register
+    case 8:
+      Opcode = X86::MOV32ri;
+      Reg = getAliasSized(Reg, 4);
+      break;
     default:
       llvm_unreachable("Unexpected size");
     }