From: Jeff Law <law@redhat.com>
Date: Wed, 5 Mar 1997 22:04:31 +0000 (+0000)
Subject:         * simops.c: Fix register references when computing Z and N bits
X-Git-Tag: gdb-4_18~6244
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=43eb4bed5097d56ee104c5be80825675e532c230;p=external%2Fbinutils.git

    * simops.c: Fix register references when computing Z and N bits
        for lsr imm8,dn.
Bug exposed by c-torture testing of the mn10300.
---

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index caa2d75..6ed254f 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2154,7 +2154,7 @@ void OP_F2A0 (insn, extension)
   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }
 
-/* lsr dm, dn */
+/* lsr imm8, dn */
 void OP_F8C400 (insn, extension)
      unsigned long insn, extension;
 {
@@ -2162,8 +2162,8 @@ void OP_F8C400 (insn, extension)
 
   c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
   State.regs[REG_D0 + REG0_8 (insn)] >>=  (insn & 0xff);
-  z = (State.regs[REG_D0 + (REG0 (insn) >> 8)] == 0);
-  n = (State.regs[REG_D0 + (REG0 (insn) >> 8)] & 0x80000000) != 0;
+  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C);
   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }