From: Olav Haugan Date: Mon, 4 Aug 2014 18:01:02 +0000 (+0100) Subject: iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1 X-Git-Tag: upstream/snapshot3+hdmi~1564 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=433ec1a32c7380567c38226a6c490fd899339017;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1 commit 1fc870c7efa364862c3bc792cfbdb38afea26742 upstream. Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it is only applicable to stage-2 context banks. This patch ensures that we don't set the reserved TCR bits for stage-1 translations. Signed-off-by: Olav Haugan Signed-off-by: Will Deacon Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 1d9ab39..2ecac46 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -794,8 +794,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg |= TTBCR_EAE | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | - (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | - (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); + + if (!stage1) + reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); + writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); /* MAIR0 (stage-1 only) */