From: Palmer Dabbelt Date: Wed, 21 Jun 2023 14:49:09 +0000 (-0700) Subject: Merge patch series "ISA string parser cleanups" X-Git-Tag: v6.6.7~2493^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=42b89447b65863904eaf802ee05b55a238eac538;p=platform%2Fkernel%2Flinux-starfive.git Merge patch series "ISA string parser cleanups" Conor Dooley says: From: Conor Dooley Here are some bits that were discussed with Drew on the "should we allow caps" threads that I have now created patches for: - splitting of riscv_of_processor_hartid() into two distinct functions, one for use purely during early boot, prior to the establishment of the possible-cpus mask & another to fit the other current use-cases - that then allows us to then completely skip some validation of the hartid in the parser - the biggest diff in the series is a rework of the comments in the parser, as I have mostly found the existing (sparse) ones to not be all that helpful whenever I have to go back and look at it - from writing the comments, I found a conditional doing a bit of a dance that I found counter-intuitive, so I've had a go at making that match what I would expect a little better - `i` implies 4 other extensions, so add them as extensions and set them for the craic. Sure why not like... * b4-shazam-merge: RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing Link: https://lore.kernel.org/r/20230607-audacity-overhaul-82bb867a825f@spud Signed-off-by: Palmer Dabbelt --- 42b89447b65863904eaf802ee05b55a238eac538 diff --cc arch/riscv/include/asm/hwcap.h index bdd614d,e0eb9ad..f041bfa --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@@ -47,8 -46,10 +47,12 @@@ #define RISCV_ISA_EXT_ZICBOZ 34 #define RISCV_ISA_EXT_SMAIA 35 #define RISCV_ISA_EXT_SSAIA 36 -#define RISCV_ISA_EXT_ZICNTR 37 -#define RISCV_ISA_EXT_ZICSR 38 -#define RISCV_ISA_EXT_ZIFENCEI 39 -#define RISCV_ISA_EXT_ZIHPM 40 +#define RISCV_ISA_EXT_ZBA 37 +#define RISCV_ISA_EXT_ZBS 38 ++#define RISCV_ISA_EXT_ZICNTR 39 ++#define RISCV_ISA_EXT_ZICSR 40 ++#define RISCV_ISA_EXT_ZIFENCEI 41 ++#define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --cc arch/riscv/kernel/cpu.c index e58e93d,6aea641..a2fc952 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@@ -186,10 -208,12 +208,14 @@@ arch_initcall(riscv_cpuinfo_init) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --cc arch/riscv/kernel/cpufeature.c index f8dc577,d21f7e8..bdcf460 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@@ -129,9 -124,8 +129,8 @@@ void __init riscv_fill_hwcap(void } for_each_possible_cpu(cpu) { + struct riscv_isainfo *isainfo = &hart_isa[cpu]; unsigned long this_hwcap = 0; - const char *temp; - DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); if (acpi_disabled) { node = of_cpu_device_node_get(cpu); @@@ -154,15 -148,16 +153,15 @@@ } } - temp = isa; - if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4)) - isa += 4; - else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4)) - isa += 4; - /* The riscv,isa DT property must start with rv64 or rv32 */ - if (temp == isa) - continue; - for (; *isa; ++isa) { + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ + isa += 4; + - bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); + while (*isa) { const char *ext = isa++; const char *ext_end = isa; bool ext_long = false, ext_err = false; @@@ -273,6 -312,23 +318,23 @@@ } /* + * Linux requires the following extensions, so we may as well + * always set them. + */ - set_bit(RISCV_ISA_EXT_ZICSR, this_isa); - set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); ++ set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa); ++ set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa); + + /* + * These ones were as they were part of the base ISA when the + * port & dt-bindings were upstreamed, and so can be set + * unconditionally where `i` is in riscv,isa on DT systems. + */ + if (acpi_disabled) { - set_bit(RISCV_ISA_EXT_ZICNTR, this_isa); - set_bit(RISCV_ISA_EXT_ZIHPM, this_isa); ++ set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa); ++ set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); + } + + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't * have.