From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Thu, 22 May 2008 10:13:38 +0000 (+0000)
Subject: lahf/sahf cpuid test
X-Git-Tag: TizenStudio_2.0_p2.3~11702
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=428db4c05accc7d52174e1595ec86e0d828c29e5;p=sdk%2Femulator%2Fqemu.git

lahf/sahf cpuid test

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4523 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-i386/TODO b/target-i386/TODO
index 1a1bf56..9fd1bbe 100644
--- a/target-i386/TODO
+++ b/target-i386/TODO
@@ -1,16 +1,10 @@
 Correctness issues:
 
 - some eflags manipulation incorrectly reset the bit 0x2.
-- rework eflags optimization (will be a consequence of TCG port)
 - SVM: rework the implementation: simplify code, move most intercept
   tests as dynamic, correct segment access, verify exception safety,
   cpu save/restore, SMM save/restore. 
-- x86_64: fxsave/fxrestore intel/amd differences
 - x86_64: lcall/ljmp intel/amd differences ?
-- x86_64: cmpxchgl intel/amd differences ?
-- x86_64: cmovl intel/amd differences ?
-- cmpxchg16b + cmpxchg8b cpuid test
-- x86: monitor invalid 
 - better code fetch (different exception handling + CS.limit support)
 - user/kernel PUSHL/POPL in helper.c
 - add missing cpuid tests
@@ -27,11 +21,12 @@ Correctness issues:
 
 Optimizations/Features:
 
-- finish TCG port
 - add SVM nested paging support
 - add VMX support
 - add AVX support
 - add SSE5 support
+- fxsave/fxrstor AMD extensions
+- improve monitor/mwait support
 - faster EFLAGS update: consider SZAP, C, O can be updated separately
   with a bit field in CC_OP and more state variables.
 - evaluate x87 stack pointer statically
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6e55930..04db898 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -103,6 +103,7 @@ typedef struct DisasContext {
     int cpuid_features;
     int cpuid_ext_features;
     int cpuid_ext2_features;
+    int cpuid_ext3_features;
 } DisasContext;
 
 static void gen_eob(DisasContext *s);
@@ -5829,7 +5830,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x9e: /* sahf */
-        if (CODE64(s))
+        if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
             goto illegal_op;
         gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
         if (s->cc_op != CC_OP_DYNAMIC)
@@ -5841,7 +5842,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         s->cc_op = CC_OP_EFLAGS;
         break;
     case 0x9f: /* lahf */
-        if (CODE64(s))
+        if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
             goto illegal_op;
         if (s->cc_op != CC_OP_DYNAMIC)
             gen_op_set_cc_op(s->cc_op);
@@ -7058,6 +7059,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
     dc->cpuid_features = env->cpuid_features;
     dc->cpuid_ext_features = env->cpuid_ext_features;
     dc->cpuid_ext2_features = env->cpuid_ext2_features;
+    dc->cpuid_ext3_features = env->cpuid_ext3_features;
 #ifdef TARGET_X86_64
     dc->lma = (flags >> HF_LMA_SHIFT) & 1;
     dc->code64 = (flags >> HF_CS64_SHIFT) & 1;