From: Francisco Jerez <currojerez@riseup.net>
Date: Thu, 7 Jul 2022 21:43:05 +0000 (-0700)
Subject: intel/fs/xe2+: Fixes for increased accumulator register width.
X-Git-Tag: upstream/23.3.3~1809
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=421d43fe62f6ac2dd616a4b16089fe54c69ffe31;p=platform%2Fupstream%2Fmesa.git

intel/fs/xe2+: Fixes for increased accumulator register width.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
---

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 385b4bf..2306786 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4413,7 +4413,9 @@ fs_visitor::lower_mul_qword_inst(fs_inst *inst, bblock_t *block)
    } else {
       fs_reg bd_high(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
       fs_reg bd_low(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD);
-      fs_reg acc = retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD);
+      const unsigned acc_width = reg_unit(devinfo) * 8;
+      fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD),
+                             inst->group % acc_width);
 
       fs_inst *mul = ibld.MUL(acc,
                             subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
@@ -4469,7 +4471,9 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
 
    /* Should have been lowered to 8-wide. */
    assert(inst->exec_size <= get_lowered_simd_width(compiler, inst));
-   const fs_reg acc = retype(brw_acc_reg(inst->exec_size), inst->dst.type);
+   const unsigned acc_width = reg_unit(devinfo) * 8;
+   const fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), inst->dst.type),
+                                inst->group % acc_width);
    fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);
    fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]);
 
diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index 01a8a1a..00c34c0 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -1345,7 +1345,7 @@ namespace {
              inst->writes_accumulator_implicitly(devinfo));
       const unsigned offset = (inst->group + i) * type_sz(tx) *
          (devinfo->ver < 7 || brw_reg_type_is_floating_point(tx) ? 1 : 2);
-      return offset / REG_SIZE % 2;
+      return offset / (reg_unit(devinfo) * REG_SIZE) % 2;
    }
 
    /**