From: Conor Dooley Date: Thu, 27 Apr 2023 10:43:42 +0000 (+0100) Subject: dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support X-Git-Tag: v6.6.17~4912^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=41ebfc91f785c202e8e8f9bd2f67154efad6287e;p=platform%2Fkernel%2Flinux-rpi.git dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support The dt-binding was defined before the extraction of csr access and fence.i into their own extensions, and thus the presence of the I base extension implies Zicsr and Zifencei. There's no harm in adding them obviously, but for backwards compatibility with DTs that existed prior to that extraction, software is unable to differentiate between "i" and "i_zicsr_zifencei" without any further information. Signed-off-by: Conor Dooley Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230427-fence-blurred-c92fb69d4137@wendy Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 25d6e8d..3d2934b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -86,6 +86,12 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ + Due to revisions of the ISA specification, some deviations + have arisen over time. + Notably, riscv,isa was defined prior to the creation of the + Zicsr and Zifencei extensions and thus "i" implies + "zicsr_zifencei". + While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing.