From: Jaehoon Chung Date: Thu, 24 Feb 2011 04:46:11 +0000 (+0900) Subject: mmc: dw_mmc: support DDR mode X-Git-Tag: v2.6.39-rc1~412^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=41babf753cc82ab6208903625a084bf305c32d06;p=profile%2Fivi%2Fkernel-adaptation-intel-automotive.git mmc: dw_mmc: support DDR mode This patch adds DDR mode support to dw_mmc. If we set any bit in UHS_REG bit[16:31], the card of that slot is supported for DDR mode. For example, if UHS_REG[16] is set, card number 0 is DDR mode. Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Acked-by: Will Newton Signed-off-by: Chris Ball --- diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 62c8440..58476c1 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -662,6 +662,7 @@ static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct dw_mci_slot *slot = mmc_priv(mmc); + u32 regs; /* set default 1 bit mode */ slot->ctype = SDMMC_CTYPE_1BIT; @@ -678,6 +679,13 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } + /* DDR mode set */ + if (ios->ddr) { + regs = mci_readl(slot->host, UHS_REG); + regs |= (0x1 << slot->id) << 16; + mci_writel(slot->host, UHS_REG, regs); + } + if (ios->clock) { /* * Use mirror of ios->clock to prevent race with mmc diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 5dd55a7..23c662a 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -43,6 +43,7 @@ #define SDMMC_USRID 0x068 #define SDMMC_VERID 0x06c #define SDMMC_HCON 0x070 +#define SDMMC_UHS_REG 0x074 #define SDMMC_BMOD 0x080 #define SDMMC_PLDMND 0x084 #define SDMMC_DBADDR 0x088 @@ -51,7 +52,6 @@ #define SDMMC_DSCADDR 0x094 #define SDMMC_BUFADDR 0x098 #define SDMMC_DATA 0x100 -#define SDMMC_DATA_ADR 0x100 /* shift bit field */ #define _SBF(f, v) ((v) << (f))