From: Samuel Holland <samuel@sholland.org>
Date: Mon, 15 Aug 2022 05:08:05 +0000 (-0500)
Subject: dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
X-Git-Tag: v6.6.17~6037^2~28^2^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=41adc2fbad8bc42ed5fdf480e5318133a4941bbb;p=platform%2Fkernel%2Flinux-rpi.git

dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cab..e98a716 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,8 @@ properties:
               - sifive,u5
               - sifive,u7
               - canaan,k210
+              - thead,c906
+              - thead,c910
           - const: riscv
       - items:
           - enum: