From: Kristian H. Kristensen Date: Tue, 22 Oct 2019 23:33:18 +0000 (-0700) Subject: freedreno/ir3: Add ir3 intrinsics for tessellation X-Git-Tag: upstream/20.1.8~6204 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=41984c84227a37b6836a57a39348c70b49457212;p=platform%2Fupstream%2Fmesa.git freedreno/ir3: Add ir3 intrinsics for tessellation These provide the iovas for system memory buffers used for tessellation as well as a new HW specific system value. Signed-off-by: Kristian H. Kristensen Acked-by: Eric Anholt Reviewed-by: Rob Clark --- diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 9c1418f..55050a9 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -792,6 +792,12 @@ system_value("vs_vertex_stride_ir3", 1) system_value("gs_header_ir3", 1) system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) +# System values for freedreno tessellation shaders. +system_value("hs_patch_stride_ir3", 1) +system_value("tess_factor_base_ir3", 2) +system_value("tess_param_base_ir3", 2) +system_value("tcs_header_ir3", 1) + # IR3-specific load/store intrinsics. These access a buffer used to pass data # between geometry stages - perhaps it's explicit access to the vertex cache. diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c index afaad50..7b908ea 100644 --- a/src/compiler/shader_enums.c +++ b/src/compiler/shader_enums.c @@ -255,6 +255,7 @@ gl_system_value_name(gl_system_value sysval) ENUM(SYSTEM_VALUE_BARYCENTRIC_CENTROID), ENUM(SYSTEM_VALUE_BARYCENTRIC_SIZE), ENUM(SYSTEM_VALUE_GS_HEADER_IR3), + ENUM(SYSTEM_VALUE_TCS_HEADER_IR3), }; STATIC_ASSERT(ARRAY_SIZE(names) == SYSTEM_VALUE_MAX); return NAME(sysval); diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h index f9b2b8c..07f96f3 100644 --- a/src/compiler/shader_enums.h +++ b/src/compiler/shader_enums.h @@ -642,11 +642,12 @@ typedef enum SYSTEM_VALUE_BARYCENTRIC_SIZE, /** - * IR3 specific geometry shader system value that packs invocation id, - * thread id and vertex id. Having this as a nir level system value lets - * us do the unpacking in nir. + * IR3 specific geometry shader and tesselation control shader system + * values that packs invocation id, thread id and vertex id. Having this + * as a nir level system value lets us do the unpacking in nir. */ SYSTEM_VALUE_GS_HEADER_IR3, + SYSTEM_VALUE_TCS_HEADER_IR3, SYSTEM_VALUE_MAX /**< Number of values */ } gl_system_value; diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index f7af73f..f4e9433 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1363,6 +1363,21 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_load_vs_vertex_stride_ir3: dst[0] = create_uniform(b, primitive_param + 1); break; + case nir_intrinsic_load_hs_patch_stride_ir3: + dst[0] = create_uniform(b, primitive_param + 2); + break; + case nir_intrinsic_load_patch_vertices_in: + dst[0] = create_uniform(b, primitive_param + 3); + break; + case nir_intrinsic_load_tess_param_base_ir3: + dst[0] = create_uniform(b, primitive_param + 4); + dst[1] = create_uniform(b, primitive_param + 5); + break; + case nir_intrinsic_load_tess_factor_base_ir3: + dst[0] = create_uniform(b, primitive_param + 6); + dst[1] = create_uniform(b, primitive_param + 7); + break; + case nir_intrinsic_load_primitive_location_ir3: idx = nir_intrinsic_driver_location(intr); dst[0] = create_uniform(b, primitive_map + idx); @@ -1371,6 +1386,9 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_load_gs_header_ir3: dst[0] = ctx->gs_header; break; + case nir_intrinsic_load_tcs_header_ir3: + dst[0] = ctx->tcs_header; + break; case nir_intrinsic_load_primitive_id: dst[0] = ctx->primitive_id; diff --git a/src/freedreno/ir3/ir3_context.h b/src/freedreno/ir3/ir3_context.h index 2a1f907..bb283a7 100644 --- a/src/freedreno/ir3/ir3_context.h +++ b/src/freedreno/ir3/ir3_context.h @@ -80,6 +80,11 @@ struct ir3_context { struct ir3_instruction *primitive_id; struct ir3_instruction *gs_header; + /* For tessellation shaders: */ + struct ir3_instruction *patch_vertices_in; + struct ir3_instruction *tcs_header; + struct ir3_instruction *tess_coord; + /* Compute shader inputs: */ struct ir3_instruction *local_invocation_id, *work_group_id; diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index 0cfb28e..4260aee 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -363,6 +363,8 @@ output_name(struct ir3_shader_variant *so, int i) return "GS_HEADER"; case VARYING_SLOT_GS_VERTEX_FLAGS_IR3: return "GS_VERTEX_FLAGS"; + case VARYING_SLOT_TCS_HEADER_IR3: + return "TCS_HEADER"; default: return gl_varying_slot_name(so->outputs[i].slot); } diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index dd613f2..84a7807 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -738,6 +738,7 @@ ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot) #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0) #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1) +#define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2) static inline uint32_t