From: Chris Wilson Date: Mon, 14 Feb 2011 15:56:14 +0000 (+0000) Subject: Remove confusing use of IS_9XX X-Git-Tag: 1.1~230 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=41570d9bf583d35687bab88ac88620af41404836;p=platform%2Fupstream%2Fintel-gpu-tools.git Remove confusing use of IS_9XX ... and test for what we mean instead. Reported-by: Diego Celix Signed-off-by: Chris Wilson --- diff --git a/lib/instdone.c b/lib/instdone.c index 305f361..3e4d895 100644 --- a/lib/instdone.c +++ b/lib/instdone.c @@ -275,7 +275,7 @@ init_instdone_definitions(uint32_t devid) } else { init_g965_instdone1(); } - } else if (IS_9XX(devid)) { + } else if (IS_GEN3(devid)) { gen3_instdone_bit(IDCT_DONE, "IDCT"); gen3_instdone_bit(IQ_DONE, "IQ"); gen3_instdone_bit(PR_DONE, "PR"); diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 48c441d..d1e5088 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -125,10 +125,6 @@ devid == PCI_CHIP_I946_GZ || \ IS_G4X(devid)) -#define IS_965(devid) (IS_GEN4(devid) || \ - IS_GEN5(devid) || \ - IS_GEN6(devid)) - #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) #define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ @@ -139,9 +135,8 @@ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ devid == PCI_CHIP_SANDYBRIDGE_S) -#define IS_9XX(devid) (IS_GEN3(devid) || \ - IS_GEN4(devid) || \ - IS_GEN4(devid) || \ +#define IS_965(devid) (IS_GEN4(devid) || \ + IS_GEN5(devid) || \ IS_GEN6(devid)) #define IS_INTEL(devid) (IS_GEN2(devid) || \ diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c index faaeeef..0228a87 100644 --- a/lib/intel_mmio.c +++ b/lib/intel_mmio.c @@ -71,10 +71,10 @@ intel_get_mmio(struct pci_device *pci_dev) int err; devid = pci_dev->device_id; - if (IS_9XX(devid)) - mmio_bar = 0; - else + if (IS_GEN2(devid)) mmio_bar = 1; + else + mmio_bar = 0; err = pci_device_map_range (pci_dev, pci_dev->regions[mmio_bar].base_addr, diff --git a/tools/intel_decode.c b/tools/intel_decode.c index 971473f..b344e21 100644 --- a/tools/intel_decode.c +++ b/tools/intel_decode.c @@ -891,7 +891,7 @@ decode_3d_1d(uint32_t *data, int count, BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_1"); /* save vertex state for decode */ - if (IS_9XX(devid)) { + if (!IS_GEN2(devid)) { if (word == 2) { saved_s2_set = 1; saved_s2 = data[i]; @@ -1023,7 +1023,7 @@ decode_3d_1d(uint32_t *data, int count, } return len; case 0x01: - if (!IS_9XX(devid)) + if (IS_GEN2(devid)) break; instr_out(data, hw_offset, 0, "3DSTATE_SAMPLER_STATE\n"); instr_out(data, hw_offset, 1, "mask\n"); @@ -1109,7 +1109,7 @@ decode_3d_1d(uint32_t *data, int count, for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) { opcode_3d_1d = &opcodes_3d_1d[idx]; - if (opcode_3d_1d->i830_only && IS_9XX(devid)) + if (opcode_3d_1d->i830_only && !IS_GEN2(devid)) continue; if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) { @@ -2333,7 +2333,7 @@ intel_decode(uint32_t *data, int count, index += decode_3d_965(data + index, count - index, hw_offset + index * 4, devid, &failures); - } else if (IS_9XX(devid)) { + } else if (IS_GEN3(devid)) { index += decode_3d(data + index, count - index, hw_offset + index * 4, devid, &failures); diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index a27ade9..2745019 100644 --- a/tools/intel_error_decode.c +++ b/tools/intel_error_decode.c @@ -202,7 +202,7 @@ print_pgtbl_err(unsigned int reg, unsigned int devid) { if (IS_965(devid)) { return print_i965_pgtbl_err(reg); - } else if (IS_9XX(devid)) { + } else if (IS_GEN3(devid)) { return print_i915_pgtbl_err(reg); } else { return print_i830_pgtbl_err(reg); @@ -268,7 +268,7 @@ read_data_file (FILE *file) devid = reg; if (IS_965(devid)) { printf("Detected i965+ chipset\n"); - } else if (IS_9XX(devid)) { + } else if (IS_GEN3(devid)) { printf("Detected i9xx chipset\n"); } else { printf("Detected i8xx chipset\n"); diff --git a/tools/intel_gtt.c b/tools/intel_gtt.c index bc6d222..4927b7e 100644 --- a/tools/intel_gtt.c +++ b/tools/intel_gtt.c @@ -51,7 +51,7 @@ int main(int argc, char **argv) devid = pci_dev->device_id; intel_get_mmio(pci_dev); - if (!IS_9XX(devid)) { + if (IS_GEN2(devid)) { printf("Unsupported chipset for gtt dumper\n"); exit(1); } diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index 27af525..4c44dc6 100644 --- a/tools/intel_reg_dumper.c +++ b/tools/intel_reg_dumper.c @@ -349,25 +349,7 @@ DEBUGSTRING(i830_debug_dpll) char sdvoextra[20]; int p1, p2 = 0; - if (IS_9XX(devid)) { - if (IS_IGD(devid)) { - p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> - DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); - } else { - p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> - DPLL_FPA01_P1_POST_DIV_SHIFT); - } - switch (val & DPLL_MODE_MASK) { - case DPLLB_MODE_DAC_SERIAL: - mode = "DAC/serial"; - p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10; - break; - case DPLLB_MODE_LVDS: - mode = "LVDS"; - p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14; - break; - } - } else { + if (IS_GEN2(devid)) { char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B); if (is_lvds) { @@ -394,6 +376,24 @@ DEBUGSTRING(i830_debug_dpll) else p2 = 2; } + } else { + if (IS_IGD(devid)) { + p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> + DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); + } else { + p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> + DPLL_FPA01_P1_POST_DIV_SHIFT); + } + switch (val & DPLL_MODE_MASK) { + case DPLLB_MODE_DAC_SERIAL: + mode = "DAC/serial"; + p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10; + break; + case DPLLB_MODE_LVDS: + mode = "LVDS"; + p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14; + break; + } } switch (val & PLL_REF_INPUT_MASK) { @@ -1787,7 +1787,65 @@ intel_dump_regs(void) for (pipe = 0; pipe <= 1; pipe++) { fp = INREG(pipe == 0 ? FPA0 : FPB0); dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B); - if (IS_9XX(devid)) { + if (IS_GEN2(devid)) { + uint32_t lvds = INREG(LVDS); + if (devid == PCI_CHIP_I855_GM && + (lvds & LVDS_PORT_EN) && + (lvds & LVDS_PIPEB_SELECT) == (pipe << 30)) { + if ((lvds & LVDS_CLKB_POWER_MASK) == + LVDS_CLKB_POWER_UP) + p2 = 7; + else + p2 = 14; + switch ((dpll >> 16) & 0x3f) { + case 0x01: + p1 = 1; + break; + case 0x02: + p1 = 2; + break; + case 0x04: + p1 = 3; + break; + case 0x08: + p1 = 4; + break; + case 0x10: + p1 = 5; + break; + case 0x20: + p1 = 6; + break; + default: + p1 = 1; + printf("LVDS P1 0x%x invalid encoding\n", + (dpll >> 16) & 0x3f); + break; + } + } else { + if (dpll & (1 << 23)) + p2 = 4; + else + p2 = 2; + if (dpll & PLL_P1_DIVIDE_BY_TWO) + p1 = 2; + else + p1 = ((dpll >> 16) & 0x3f) + 2; + } + + switch ((dpll >> 13) & 0x3) { + case 0: + ref = 48000; + break; + case 3: + ref = 66000; + break; + default: + ref = 0; + printf("ref out of range\n"); + break; + } + } else { uint32_t lvds = INREG(LVDS); if ((lvds & LVDS_PORT_EN) && (lvds & LVDS_PIPEB_SELECT) == (pipe << 30)) { @@ -1864,64 +1922,6 @@ intel_dump_regs(void) printf("ref out of range\n"); break; } - } else { - uint32_t lvds = INREG(LVDS); - if (devid == PCI_CHIP_I855_GM && - (lvds & LVDS_PORT_EN) && - (lvds & LVDS_PIPEB_SELECT) == (pipe << 30)) { - if ((lvds & LVDS_CLKB_POWER_MASK) == - LVDS_CLKB_POWER_UP) - p2 = 7; - else - p2 = 14; - switch ((dpll >> 16) & 0x3f) { - case 0x01: - p1 = 1; - break; - case 0x02: - p1 = 2; - break; - case 0x04: - p1 = 3; - break; - case 0x08: - p1 = 4; - break; - case 0x10: - p1 = 5; - break; - case 0x20: - p1 = 6; - break; - default: - p1 = 1; - printf("LVDS P1 0x%x invalid encoding\n", - (dpll >> 16) & 0x3f); - break; - } - } else { - if (dpll & (1 << 23)) - p2 = 4; - else - p2 = 2; - if (dpll & PLL_P1_DIVIDE_BY_TWO) - p1 = 2; - else - p1 = ((dpll >> 16) & 0x3f) + 2; - } - - switch ((dpll >> 13) & 0x3) { - case 0: - ref = 48000; - break; - case 3: - ref = 66000; - break; - default: - ref = 0; - printf("ref out of range\n"); - break; - } } if (IS_965(devid)) { phase = (dpll >> 9) & 0xf; diff --git a/tools/intel_reg_snapshot.c b/tools/intel_reg_snapshot.c index fcc8b81..83e76e5 100644 --- a/tools/intel_reg_snapshot.c +++ b/tools/intel_reg_snapshot.c @@ -37,10 +37,10 @@ int main(int argc, char** argv) devid = pci_dev->device_id; intel_get_mmio(pci_dev); - if (IS_9XX(devid)) - mmio_bar = 0; - else + if (IS_GEN2(devid)) mmio_bar = 1; + else + mmio_bar = 0; write(1, mmio, pci_dev->regions[mmio_bar].size);