From: Kan Liang Date: Thu, 26 Aug 2021 15:32:43 +0000 (-0700) Subject: perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints X-Git-Tag: v6.6.17~8995^2~8 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4034fb207e302cc0b1f304084d379640c1fb1436;p=platform%2Fkernel%2Flinux-rpi.git perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints SPR M3UPI have the exact same event constraints as ICX, so add the constraints. Fixes: 2a8e51eae7c8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support") Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com --- diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index cd53057..eb2c6ce 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = { static struct intel_uncore_type spr_uncore_m3upi = { SPR_UNCORE_PCI_COMMON_FORMAT(), .name = "m3upi", + .constraints = icx_uncore_m3upi_constraints, }; static struct intel_uncore_type spr_uncore_mdf = {