From: Xiang, Haihao <haihao.xiang@intel.com>
Date: Tue, 17 Jul 2012 07:05:31 +0000 (+0800)
Subject: Add support for flag register f1 on Ivy bridge
X-Git-Tag: intel-gpu-tools-1.4~632
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ffbe96c1eb35da7fbaa22d48b26d3ec56b0e31d;p=platform%2Fupstream%2Fintel-gpu-tools.git

Add support for flag register f1 on Ivy bridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---

diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h
index 543150a..e679e25 100644
--- a/assembler/src/brw_structs.h
+++ b/assembler/src/brw_structs.h
@@ -1135,7 +1135,8 @@ struct brw_instruction
 	 GLuint src0_width:3;		/* 0x001c0000 */
 	 GLuint src0_vert_stride:4;	/* 0x01e00000 */
 	 GLuint flag_subreg_nr:1;	/* 0x02000000 */
-	 GLuint pad:6;			/* 0xfc000000 */
+	 GLuint flag_reg_nr:1;		/* 0x04000000 */
+	 GLuint pad:5;			/* 0xf8000000 */
       } da1;
 
       struct
@@ -1149,7 +1150,8 @@ struct brw_instruction
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad:6;	
+	 GLuint flag_reg_nr:1;
+	 GLuint pad:5;	
       } ia1;
 
       struct
@@ -1166,7 +1168,8 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad1:6;
+	 GLuint flag_reg_nr:1;
+	 GLuint pad1:5;
       } da16;
 
       struct
@@ -1183,7 +1186,8 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad1:6;
+	 GLuint flag_reg_nr:1;
+	 GLuint pad1:5;
       } ia16;
 
        struct 
diff --git a/assembler/src/disasm.c b/assembler/src/disasm.c
index 9d9dfac..1ec6ae5 100644
--- a/assembler/src/disasm.c
+++ b/assembler/src/disasm.c
@@ -779,7 +779,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
     if (inst->header.predicate_control) {
 	string (file, "(");
 	err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
-	string (file, "f0");
+	format (file, "f%d", inst->bits2.da1.flag_reg_nr);
 	if (inst->bits2.da1.flag_subreg_nr)
 	    format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
 	if (inst->header.access_mode == BRW_ALIGN_1)
diff --git a/assembler/src/gen4asm.h b/assembler/src/gen4asm.h
index 5dccaba..680a0a4 100644
--- a/assembler/src/gen4asm.h
+++ b/assembler/src/gen4asm.h
@@ -49,6 +49,7 @@ struct direct_reg {
 
 struct condition {
     	int cond;
+	int flag_reg_nr;
 	int flag_subreg_nr;
 };
 
diff --git a/assembler/src/gram.y b/assembler/src/gram.y
index 022fca1..60b5e84 100644
--- a/assembler/src/gram.y
+++ b/assembler/src/gram.y
@@ -389,8 +389,10 @@ unaryinstruction:
 		  if (set_instruction_src0(&$$, &$7) != 0)
 		    YYERROR;
 
-		  if ($3.flag_subreg_nr != -1)
+		  if ($3.flag_subreg_nr != -1) {
+		    $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
 		    $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
+		  }
 
 		  if (gen_level < 6 && 
 				get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@@ -419,8 +421,10 @@ binaryinstruction:
 		  if (set_instruction_src1(&$$, &$8) != 0)
 		    YYERROR;
 
-		  if ($3.flag_subreg_nr != -1)
+		  if ($3.flag_subreg_nr != -1) {
+		    $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
 		    $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
+		  }
 
 		  if (gen_level < 6 && 
 				get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@@ -449,8 +453,10 @@ binaryaccinstruction:
 		  if (set_instruction_src1(&$$, &$8) != 0)
 		    YYERROR;
 
-		  if ($3.flag_subreg_nr != -1)
+		  if ($3.flag_subreg_nr != -1) {
+		    $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
 		    $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
+		  }
 
 		  if (gen_level < 6 && 
 				get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@@ -1849,7 +1855,8 @@ accreg:		ACCREG subregnum
 
 flagreg:	FLAGREG subregnum
 		{
-		  if ($1 > 0) {
+		  if ((gen_level <= 6 && $1) > 0 ||
+		      (gen_level > 6 && $1 > 1)) {
                     fprintf(stderr,
 			    "flag register number %d out of range\n", $1);
 		    YYERROR;
@@ -2291,6 +2298,7 @@ imm32:		exp { $$.r = imm32_d; $$.u.d = $1; }
 predicate:	/* empty */
 		{
 		  $$.header.predicate_control = BRW_PREDICATE_NONE;
+		  $$.bits2.da1.flag_reg_nr = 0;
 		  $$.bits2.da1.flag_subreg_nr = 0;
 		  $$.header.predicate_inverse = 0;
 		}
@@ -2301,6 +2309,7 @@ predicate:	/* empty */
 		   * set a predicate for one flag register and conditional
 		   * modification on the other flag register.
 		   */
+		  $$.bits2.da1.flag_reg_nr = ($3.reg_nr & 0xF);
 		  $$.bits2.da1.flag_subreg_nr = $3.subreg_nr;
 		  $$.header.predicate_inverse = $2;
 		}
@@ -2360,11 +2369,13 @@ saturate:	/* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
 conditionalmodifier: condition 
 		{
 		    $$.cond = $1;
+		    $$.flag_reg_nr = 0;
 		    $$.flag_subreg_nr = -1;
 		}
 		| condition DOT flagreg
 		{
 		    $$.cond = $1;
+		    $$.flag_reg_nr = ($3.reg_nr & 0xF);
 		    $$.flag_subreg_nr = $3.subreg_nr;
 		}
 
@@ -2848,6 +2859,7 @@ void set_instruction_predicate(struct brw_instruction *instr,
 {
 	instr->header.predicate_control = predicate->header.predicate_control;
 	instr->header.predicate_inverse = predicate->header.predicate_inverse;
+	instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr;
 	instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr;
 }