From: Inki Dae <inki.dae@samsung.com>
Date: Fri, 23 Nov 2018 07:18:36 +0000 (+0900)
Subject: ARM: dts: exynos: change vpll clock to 600MHz
X-Git-Tag: submit/tizen/20190329.020226~209
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3f1ff33b6c0d973342bf9feefcf9921935df7d54;p=platform%2Fkernel%2Flinux-exynos.git

ARM: dts: exynos: change vpll clock to 600MHz

This change enhances MALI inference(on-device deep leanring) performance.

Change-Id: I2a9341589873a049bd91ee6771c96d831768df3c
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6ebd184ce5e3..652274eaf7b3 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -422,6 +422,8 @@
 
 &mali {
 	mali-supply = <&buck4_reg>;
+	assigned-clocks = <&clock CLK_FOUT_VPLL>;
+	assigned-clock-rates = <600000000>;
 	status = "okay";
 };