From: gavin Date: Tue, 26 Oct 1999 20:29:35 +0000 (+0000) Subject: * config/mips/mips.h (ISA_HAS_64BIT_REGS,ISA_HAS_BRANCHLIKELY, X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3edb38b871b622dd734c54aeba8dcbc13a89c7fd;p=platform%2Fupstream%2Flinaro-gcc.git * config/mips/mips.h (ISA_HAS_64BIT_REGS,ISA_HAS_BRANCHLIKELY, ISA_HAS_FP4,ISA_HAS_CONDMOVE): New. (GENERATE_BRANCHLIKELY,HAVE_SQRT_P, CONDITIONAL_REGISTER_USEAGE): Use them. * config/mips/mips.c (mips_move_1word,mips_move_2words, gen_conditional_branch,override_options) : Use them. * config/mips/mips.md : Use them. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30199 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0326679..7c42211 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +1999-10-26 Gavin Romig-Koch + + * config/mips/mips.h (ISA_HAS_64BIT_REGS,ISA_HAS_BRANCHLIKELY, + ISA_HAS_FP4,ISA_HAS_CONDMOVE): New. + (GENERATE_BRANCHLIKELY,HAVE_SQRT_P, + CONDITIONAL_REGISTER_USEAGE): Use them. + * config/mips/mips.c (mips_move_1word,mips_move_2words, + gen_conditional_branch,override_options) : Use them. + * config/mips/mips.md : Use them. + Tue Oct 26 13:09:23 1999 Richard Henderson * i386.md (zero_extendqihi2): Use SImode register name with andl. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 75e7421..9be617f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1719,7 +1719,7 @@ mips_move_1word (operands, insn, unsignedp) ret = "mflo\t%0"; } - else if (ST_REG_P (regno1) && mips_isa >= 4) + else if (ST_REG_P (regno1) && ISA_HAS_FP4) ret = "li\t%0,1\n\tmovf\t%0,%.,%1"; else @@ -1728,7 +1728,7 @@ mips_move_1word (operands, insn, unsignedp) if (FP_REG_P (regno1)) ret = "mfc1\t%0,%1"; - else if (regno1 == FPSW_REGNUM && mips_isa < 4) + else if (regno1 == FPSW_REGNUM && ! ISA_HAS_FP4) ret = "cfc1\t%0,$31"; } } @@ -1755,7 +1755,7 @@ mips_move_1word (operands, insn, unsignedp) } } - else if (regno0 == FPSW_REGNUM && mips_isa < 4) + else if (regno0 == FPSW_REGNUM && ! ISA_HAS_FP4) { if (GP_REG_P (regno1)) { @@ -2218,7 +2218,9 @@ mips_move_2words (operands, insn) or higher. For !TARGET_64BIT && gp registers we need to avoid this by using two li instructions instead. */ - if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0)) + if (ISA_HAS_64BIT_REGS + && ! TARGET_64BIT + && ! FP_REG_P (regno0)) { split_double (op1, operands + 2, operands + 3); ret = "li\t%0,%2\n\tli\t%D0,%3"; @@ -2871,7 +2873,7 @@ gen_conditional_branch (operands, test_code) case CMP_SF: case CMP_DF: - if (mips_isa < 4) + if (! ISA_HAS_FP4) reg = gen_rtx_REG (CCmode, FPSW_REGNUM); else reg = gen_reg_rtx (CCmode); @@ -4363,7 +4365,7 @@ override_options () if (mips_abi_string == 0 && mips_isa_string && mips_abi != ABI_EABI && mips_abi != ABI_O64) { - if (mips_isa <= 2) + if (! ISA_HAS_64BIT_REGS) mips_abi = ABI_32; else mips_abi = ABI_64; @@ -4384,9 +4386,9 @@ override_options () /* If both ABI and ISA were specified, check for conflicts. */ else if (mips_isa_string && mips_abi_string) { - if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64 + if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64 || mips_abi == ABI_O64)) - || (mips_isa >= 3 && mips_abi == ABI_32)) + || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32)) error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa); } @@ -4535,24 +4537,24 @@ override_options () } } - if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1) - || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2) + if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1)) + || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2) || ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R4100 || mips_cpu == PROCESSOR_R4300 || mips_cpu == PROCESSOR_R4600 || mips_cpu == PROCESSOR_R4650) - && mips_isa > 3)) + && mips_isa != 1 && mips_isa != 2 && mips_isa != 3)) error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); /* make sure sizes of ints/longs/etc. are ok */ - if (mips_isa < 3) + if (! ISA_HAS_64BIT_REGS) { if (TARGET_FLOAT64) - fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers"); + fatal ("-mips%d does not support 64 bit fp registers", mips_isa); else if (TARGET_64BIT) - fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers"); + fatal ("-mips%d does not support 64 bit gp registers", mips_isa); } if (mips_abi != ABI_32 && mips_abi != ABI_O64) @@ -4731,7 +4733,7 @@ override_options () if (mode == CCmode) { - if (mips_isa < 4) + if (! ISA_HAS_FP4) temp = (regno == FPSW_REGNUM); else temp = (ST_REG_P (regno) || GP_REG_P (regno) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index cb00702..9e64f3e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -542,7 +542,7 @@ extern void sbss_section PARAMS ((void)); /* This is meant to be redefined in the host dependent files. */ #define SUBTARGET_TARGET_OPTIONS -#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2))) +#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY)) /* Generate three-operand multiply instructions for both SImode and DImode. */ #define GENERATE_MULT3 (TARGET_MIPS3900 \ @@ -552,7 +552,19 @@ extern void sbss_section PARAMS ((void)); depending on the instruction set architecture level. */ #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY -#define HAVE_SQRT_P() (mips_isa >= 2) +#define HAVE_SQRT_P() (mips_isa != 1) + +/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */ +#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 || mips_isa == 64) + +/* ISA has branch likely instructions (eg. mips2). */ +#define ISA_HAS_BRANCHLIKELY (mips_isa != 1) + +/* ISA has the FP instructions introduced in mips4. */ +#define ISA_HAS_FP4 (mips_isa == 4) + +/* ISA has the non-FP conditional move instructions introduced in mips4. */ +#define ISA_HAS_CONDMOVE (mips_isa == 4) /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit @@ -622,7 +634,7 @@ do \ for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ fixed_regs[regno] = call_used_regs[regno] = 1; \ } \ - else if (mips_isa < 4) \ + else if (! ISA_HAS_FP4) \ { \ int regno; \ \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index fe66e4a..e2c99733 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2075,7 +2075,7 @@ (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")) (match_operand:DF 3 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "madd.d\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "DF")]) @@ -2085,7 +2085,7 @@ (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")) (match_operand:SF 3 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "madd.s\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "SF")]) @@ -2095,7 +2095,7 @@ (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")) (match_operand:DF 3 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "msub.d\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "DF")]) @@ -2106,7 +2106,7 @@ (match_operand:SF 2 "register_operand" "f")) (match_operand:SF 3 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "msub.s\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "SF")]) @@ -2116,7 +2116,7 @@ (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")) (match_operand:DF 3 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "nmadd.d\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "DF")]) @@ -2126,7 +2126,7 @@ (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")) (match_operand:SF 3 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "nmadd.s\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") (set_attr "mode" "SF")]) @@ -2136,7 +2136,7 @@ (minus:DF (match_operand:DF 1 "register_operand" "f") (mult:DF (match_operand:DF 2 "register_operand" "f") (match_operand:DF 3 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "nmsub.d\\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "DF")]) @@ -2146,7 +2146,7 @@ (minus:SF (match_operand:SF 1 "register_operand" "f") (mult:SF (match_operand:SF 2 "register_operand" "f") (match_operand:SF 3 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "nmsub.s\\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "SF")]) @@ -2181,7 +2181,7 @@ [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (match_operand:DF 1 "const_float_1_operand" "") (match_operand:DF 2 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" "recip.d\\t%0,%2" [(set_attr "type" "fdiv") (set_attr "mode" "DF")]) @@ -2190,7 +2190,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "const_float_1_operand" "") (match_operand:SF 2 "register_operand" "f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math" "recip.s\\t%0,%2" [(set_attr "type" "fdiv") (set_attr "mode" "SF")]) @@ -2782,7 +2782,7 @@ [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (match_operand:DF 1 "const_float_1_operand" "") (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" "rsqrt.d\\t%0,%2" [(set_attr "type" "fsqrt") (set_attr "mode" "DF")]) @@ -2791,7 +2791,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "const_float_1_operand" "") (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math" "rsqrt.s\\t%0,%2" [(set_attr "type" "fsqrt") (set_attr "mode" "SF")]) @@ -5565,7 +5565,7 @@ move\\t%0,%z4\\n\\ (define_insn "movcc" [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m") (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "* return mips_move_1word (operands, insn, FALSE);" [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store") (set_attr "mode" "SI") @@ -5577,7 +5577,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:CC 0 "register_operand" "=z") (match_operand:CC 1 "general_operand" "z")) (clobber (match_operand:TF 2 "register_operand" "=&f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" " { rtx source; @@ -5615,7 +5615,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:CC 0 "general_operand" "=z") (match_operand:CC 1 "register_operand" "z")) (clobber (match_operand:CC 2 "register_operand" "=&d"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" " { /* This is called when we are copying a condition code register out @@ -5657,7 +5657,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SF 0 "register_operand" "=f") (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "lwxc1\\t%0,%1(%2)" [(set_attr "type" "load") (set_attr "mode" "SF")]) @@ -5666,7 +5666,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SF 0 "register_operand" "=f") (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d") (match_operand:DI 2 "se_register_operand" "d"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "lwxc1\\t%0,%1(%2)" [(set_attr "type" "load") (set_attr "mode" "SF")]) @@ -5675,7 +5675,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DF 0 "register_operand" "=f") (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "ldxc1\\t%0,%1(%2)" [(set_attr "type" "load") (set_attr "mode" "DF")]) @@ -5684,7 +5684,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DF 0 "register_operand" "=f") (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d") (match_operand:DI 2 "se_register_operand" "d"))))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "ldxc1\\t%0,%1(%2)" [(set_attr "type" "load") (set_attr "mode" "DF")]) @@ -5693,7 +5693,7 @@ move\\t%0,%z4\\n\\ [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d"))) (match_operand:SF 0 "register_operand" "f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "swxc1\\t%0,%1(%2)" [(set_attr "type" "store") (set_attr "mode" "SF")]) @@ -5702,7 +5702,7 @@ move\\t%0,%z4\\n\\ [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d") (match_operand:DI 2 "se_register_operand" "d"))) (match_operand:SF 0 "register_operand" "f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "swxc1\\t%0,%1(%2)" [(set_attr "type" "store") (set_attr "mode" "SF")]) @@ -5711,7 +5711,7 @@ move\\t%0,%z4\\n\\ [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d"))) (match_operand:DF 0 "register_operand" "f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "sdxc1\\t%0,%1(%2)" [(set_attr "type" "store") (set_attr "mode" "DF")]) @@ -5720,7 +5720,7 @@ move\\t%0,%z4\\n\\ [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d") (match_operand:DI 2 "se_register_operand" "d"))) (match_operand:DF 0 "register_operand" "f"))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "sdxc1\\t%0,%1(%2)" [(set_attr "type" "store") (set_attr "mode" "DF")]) @@ -9924,7 +9924,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SI 2 "reg_or_0_operand" "dJ,0") (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -9939,7 +9939,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SI 2 "reg_or_0_operand" "dJ,0") (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -9955,7 +9955,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SI 1 "reg_or_0_operand" "dJ,0") (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "@ mov%T3\\t%0,%z1,%4 mov%t3\\t%0,%z2,%4" @@ -9970,7 +9970,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -9985,7 +9985,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -10001,7 +10001,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "@ mov%T3\\t%0,%z1,%4 mov%t3\\t%0,%z2,%4" @@ -10016,7 +10016,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 2 "register_operand" "f,0") (match_operand:SF 3 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "@ mov%B4.s\\t%0,%2,%1 mov%b4.s\\t%0,%3,%1" @@ -10031,7 +10031,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 2 "register_operand" "f,0") (match_operand:SF 3 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "@ mov%B4.s\\t%0,%2,%1 mov%b4.s\\t%0,%3,%1" @@ -10047,7 +10047,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 1 "register_operand" "f,0") (match_operand:SF 2 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "@ mov%T3.s\\t%0,%1,%4 mov%t3.s\\t%0,%2,%4" @@ -10062,7 +10062,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 2 "register_operand" "f,0") (match_operand:DF 3 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%B4.d\\t%0,%2,%1 mov%b4.d\\t%0,%3,%1" @@ -10077,7 +10077,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 2 "register_operand" "f,0") (match_operand:DF 3 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%B4.d\\t%0,%2,%1 mov%b4.d\\t%0,%3,%1" @@ -10093,7 +10093,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 1 "register_operand" "f,0") (match_operand:DF 2 "register_operand" "0,f")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%T3.d\\t%0,%1,%4 mov%t3.d\\t%0,%2,%4" @@ -10108,7 +10108,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:SI (match_dup 5) (match_operand:SI 2 "reg_or_0_operand" "") (match_operand:SI 3 "reg_or_0_operand" "")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE || ISA_HAS_FP4" " { gen_conditional_move (operands); @@ -10121,7 +10121,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:DI (match_dup 5) (match_operand:DI 2 "se_reg_or_0_operand" "") (match_operand:DI 3 "se_reg_or_0_operand" "")))] - "mips_isa >= 4" + "ISA_HAS_CONDMOVE || ISA_HAS_FP4" " { gen_conditional_move (operands); @@ -10134,7 +10134,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:SF (match_dup 5) (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "register_operand" "")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" " { gen_conditional_move (operands); @@ -10147,7 +10147,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:DF (match_dup 5) (match_operand:DF 2 "register_operand" "") (match_operand:DF 3 "register_operand" "")))] - "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" " { gen_conditional_move (operands);