From: Aapo Vienamo Date: Fri, 10 Aug 2018 18:13:58 +0000 (+0300) Subject: dt-bindings: mmc: Add DQS trim value to Tegra SDHCI X-Git-Tag: v5.15~7810^2~78 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ecea59d27f87b0fe9ab09b0ce8262f5355ec243;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Ulf Hansson --- diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index edecf97..32b4b4e 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186: trimmer value for non-tunable modes. - nvidia,default-trim : Specify the default outbound clock trimmer value. +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186: - The values are programmed to the Vendor Clock Control Register. Please refer to the reference manual of the SoC for correct values. + - The DQS trim values are only used on controllers which support + HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports + HS400. Example: sdhci@700b0000 {