From: Jiong Wang <jiwang@gcc.gnu.org>
Date: Fri, 1 Aug 2014 14:54:57 +0000 (+0000)
Subject: [AArch64][1/2] Fix offset glitch in load reg pair pattern
X-Git-Tag: upstream/12.2.0~61458
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3e322b3f2f5a32714ca73bc2f1846b3e7886662f;p=platform%2Fupstream%2Fgcc.git

[AArch64][1/2] Fix offset glitch in load reg pair pattern

on aarch64, we are using load register pair post-writeback instruction in
epilogue.

for example, for the following instruction:

ldp, x0, x1, [sp], #16

what it's doing is:

x0 <- MEM(sp + 0)
x1 <- MEM(sp + 8)
sp < sp + 16

while there is a glitch in our loadwb_pair* pattern, the restore of the
first reg should always be with offset zero.

(set (match_operand:GPI 2 "register_operand" "=r")
-          (mem:GPI (plus:P (match_dup 1)
-                   (match_dup 4))))
+          (mem:GPI (match_dup 1)))

gcc/
  * config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix offset.
  (loadwb_pair<GPI:mode>_<P:mode>): Likewise.
  * config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): Likewise.

From-SVN: r213485
---

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2ea55e8..8a8e8a9 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2006,10 +2006,10 @@ aarch64_gen_loadwb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
     {
     case DImode:
       return gen_loadwb_pairdi_di (base, base, reg, reg2, GEN_INT (adjustment),
-				   GEN_INT (adjustment + UNITS_PER_WORD));
+				   GEN_INT (UNITS_PER_WORD));
     case DFmode:
       return gen_loadwb_pairdf_di (base, base, reg, reg2, GEN_INT (adjustment),
-				   GEN_INT (adjustment + UNITS_PER_WORD));
+				   GEN_INT (UNITS_PER_WORD));
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f4563d1..0728fb6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1016,20 +1016,19 @@
   [(set_attr "type" "neon_store1_2reg<q>")]
 )
 
-;; Load pair with writeback.  This is primarily used in function epilogues
-;; when restoring [fp,lr]
+;; Load pair with post-index writeback.  This is primarily used in function
+;; epilogues.
 (define_insn "loadwb_pair<GPI:mode>_<P:mode>"
   [(parallel
     [(set (match_operand:P 0 "register_operand" "=k")
           (plus:P (match_operand:P 1 "register_operand" "0")
                   (match_operand:P 4 "const_int_operand" "n")))
      (set (match_operand:GPI 2 "register_operand" "=r")
-          (mem:GPI (plus:P (match_dup 1)
-                   (match_dup 4))))
+          (mem:GPI (match_dup 1)))
      (set (match_operand:GPI 3 "register_operand" "=r")
           (mem:GPI (plus:P (match_dup 1)
                    (match_operand:P 5 "const_int_operand" "n"))))])]
-  "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
+  "INTVAL (operands[5]) == GET_MODE_SIZE (<GPI:MODE>mode)"
   "ldp\\t%<w>2, %<w>3, [%1], %4"
   [(set_attr "type" "load2")]
 )
@@ -1040,18 +1039,17 @@
           (plus:P (match_operand:P 1 "register_operand" "0")
                   (match_operand:P 4 "const_int_operand" "n")))
      (set (match_operand:GPF 2 "register_operand" "=w")
-          (mem:GPF (plus:P (match_dup 1)
-                   (match_dup 4))))
+          (mem:GPF (match_dup 1)))
      (set (match_operand:GPF 3 "register_operand" "=w")
           (mem:GPF (plus:P (match_dup 1)
                    (match_operand:P 5 "const_int_operand" "n"))))])]
-  "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPF:MODE>mode)"
+  "INTVAL (operands[5]) == GET_MODE_SIZE (<GPF:MODE>mode)"
   "ldp\\t%<w>2, %<w>3, [%1], %4"
   [(set_attr "type" "neon_load1_2reg")]
 )
 
-;; Store pair with writeback.  This is primarily used in function prologues
-;; when saving [fp,lr]
+;; Store pair with pre-index writeback.  This is primarily used in function
+;; prologues.
 (define_insn "storewb_pair<GPI:mode>_<P:mode>"
   [(parallel
     [(set (match_operand:P 0 "register_operand" "=&k")