From: Tom Musta Date: Thu, 18 Dec 2014 16:34:32 +0000 (-0600) Subject: target-ppc: Power8 Supports Transactional Memory X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~396^2~14 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3e28c5e363aaf3de8b99acb662b7488ed6b49197;p=sdk%2Femulator%2Fqemu.git target-ppc: Power8 Supports Transactional Memory The Power8 processor implements the Transactional Memory Facility as defined in Power ISA 2.07. Update the initialization code to indicate this. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 1fece7b..72cc9d0 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8219,7 +8219,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64; + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_TM) | (1ull << MSR_VR) | @@ -8247,7 +8248,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX; + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;