From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Fri, 3 May 2013 20:23:44 +0000 (-0300)
Subject: drm/i915: MCH_SSKPD is a 64 bit register on Haswell
X-Git-Tag: accepted/tizen/20130614.181726~2^2~62
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3e1f72664e0a8a31e9b90c48459deb6642fd52f3;p=profile%2Fivi%2Fkernel-x86-ivi.git

drm/i915: MCH_SSKPD is a 64 bit register on Haswell

And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ad1d355..912ab4d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4633,7 +4633,7 @@ void intel_init_pm(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 		} else if (IS_HASWELL(dev)) {
-			if (SNB_READ_WM0_LATENCY()) {
+			if (I915_READ64(MCH_SSKPD)) {
 				dev_priv->display.update_wm = haswell_update_wm;
 				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
 			} else {