From: Xing Zheng Date: Wed, 18 Jan 2017 04:20:56 +0000 (+0800) Subject: clk: rockchip: fix the incorrect pclk_edp div width for RK3399 X-Git-Tag: v4.11-rc1~71^2~9^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3e1531dbc333997ae19324993119c42436d3e6b6;p=platform%2Fkernel%2Flinux-exynos.git clk: rockchip: fix the incorrect pclk_edp div width for RK3399 The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang Signed-off-by: Xing Zheng Tested-by: Lin Huang Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 3490887..73121b14 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(11), 8, GFLAGS), COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS, RK3399_CLKGATE_CON(11), 11, GFLAGS), GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(32), 12, GFLAGS),