From: Eric Christopher <echristo@gmail.com>
Date: Tue, 21 Aug 2018 18:35:08 +0000 (+0000)
Subject: Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift immediat... 
X-Git-Tag: llvmorg-8.0.0-rc1~10482
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3dc594c1e652b9225c857abde758176ba8a175b7;p=platform%2Fupstream%2Fllvm.git

Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction" due to it causing a compiler crash on valid.

This reverts commit r340016, testcase forthcoming.

llvm-svn: 340315
---

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 037c4b5..fbeea91 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1351,7 +1351,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::QBFLT:           return "PPCISD::QBFLT";
   case PPCISD::QVLFSb:          return "PPCISD::QVLFSb";
   case PPCISD::BUILD_FP128:     return "PPCISD::BUILD_FP128";
-  case PPCISD::EXTSWSLI:        return "PPCISD::EXTSWSLI";
   }
   return nullptr;
 }
@@ -14132,30 +14131,7 @@ SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
   if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
     return Value;
 
-  SDValue N0 = N->getOperand(0);
-  ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  if (!Subtarget.isISA3_0() ||
-      N0.getOpcode() != ISD::SIGN_EXTEND ||
-      N0.getOperand(0).getValueType() != MVT::i32 ||
-      CN1 == nullptr)
-    return SDValue();
-
-  // We can't save an operation here if the value is already extended, and
-  // the existing shift is easier to combine.
-  SDValue ExtsSrc = N0.getOperand(0);
-  if (ExtsSrc.getOpcode() == ISD::TRUNCATE &&
-      ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext)
-    return SDValue();
-
-  SDLoc DL(N0);
-  SDValue ShiftBy = SDValue(CN1, 0);
-  // We want the shift amount to be i32 on the extswli, but the shift could
-  // have an i64.
-  if (ShiftBy.getValueType() == MVT::i64)
-    ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32);
-
-  return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),
-                         ShiftBy);
+  return SDValue();
 }
 
 SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 3e7a4cd..f174943 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -149,10 +149,6 @@ namespace llvm {
       /// For vector types, only the last n bits are used. See vsld.
       SRL, SRA, SHL,
 
-      /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
-      /// word and shift left immediate.
-      EXTSWSLI,
-
       /// The combination of sra[wd]i and addze used to implemented signed
       /// integer division by a power of 2. The first operand is the dividend,
       /// and the second is the constant shift amount (representing the
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index b533efd..cdd57c6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -717,10 +717,9 @@ defm SRADI  : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
                          "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
                          [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
 
-defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins gprc:$rS, u6imm:$SH),
+defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
                           "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI,
-                          [(set i64:$rA, (PPCextswsli i32:$rS, (i32 imm:$SH)))]>,
-                          isPPC64, Requires<[IsISA3_0]>;
+                          []>, isPPC64;
 
 // For fast-isel:
 let isCodeGenOnly = 1, Defs = [CARRY] in
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d7e32a5..1a43037 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -114,10 +114,6 @@ def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
   SDTCisVec<0>, SDTCisPtrTy<1>
 ]>;
 
-def SDT_PPCextswsli : SDTypeProfile<1, 2, [  // extswsli
-  SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2>
-]>;
-
 //===----------------------------------------------------------------------===//
 // PowerPC specific DAG Nodes.
 //
@@ -222,8 +218,6 @@ def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
 def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
 def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
 
-def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;
-
 // Move 2 i64 values into a VSX register
 def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",
                            SDTypeProfile<1, 2,
diff --git a/llvm/test/CodeGen/PowerPC/extswsli.ll b/llvm/test/CodeGen/PowerPC/extswsli.ll
deleted file mode 100644
index 62014aa..0000000
--- a/llvm/test/CodeGen/PowerPC/extswsli.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s
-
-@z = external local_unnamed_addr global i32*, align 8
-
-; Function Attrs: norecurse nounwind readonly
-define signext i32 @_Z2tcii(i32 signext %x, i32 signext %y) local_unnamed_addr #0 {
-entry:
-  %0 = load i32*, i32** @z, align 8
-  %add = add nsw i32 %y, %x
-  %idxprom = sext i32 %add to i64
-  %arrayidx = getelementptr inbounds i32, i32* %0, i64 %idxprom
-  %1 = load i32, i32* %arrayidx, align 4
-  ret i32 %1
-; CHECK-LABEL: @_Z2tcii
-; CHECK: extswsli {{r[0-9]+}}, {{r[0-9]+}}, 2
-}