From: Paul Berry <stereotype441@gmail.com>
Date: Sat, 19 Oct 2013 20:26:27 +0000 (-0700)
Subject: i965/gs: Set force_writemask_all when setting up g0.
X-Git-Tag: upstream/10.0.5~631
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3da2c5123d043a670ebad7d01c6cba37c915b4c9;p=platform%2Fupstream%2Fmesa.git

i965/gs: Set force_writemask_all when setting up g0.

All geometry shaders begin this instruction:

    mov(1) g0.2<1>:ud 0x0:ud { align1 }

which sets up GRF0 properly for scratch reads and writes.  Since this
instruction has a SIMD size of 1, it will only have an effect if the
first channel is enabled.  In practice, the hardware seems to always
dispatch geometry shaders with the first channel enabled, but I can't
find anything in the docs to guarantee that.

So to be on the safe side, set force_writemask_all on the instruction,
which guarantees that it will have the desired effect regardless of
which channels are enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 96636e8..0893c95 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -129,14 +129,15 @@ vec4_gs_visitor::emit_prolog()
     */
    this->current_annotation = "clear r0.2";
    dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
-   emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+   inst->force_writemask_all = true;
 
    /* Create a virtual register to hold the vertex count */
    this->vertex_count = src_reg(this, glsl_type::uint_type);
 
    /* Initialize the vertex_count register to 0 */
    this->current_annotation = "initialize vertex_count";
-   vec4_instruction *inst = emit(MOV(dst_reg(this->vertex_count), 0u));
+   inst = emit(MOV(dst_reg(this->vertex_count), 0u));
    inst->force_writemask_all = true;
 
    if (c->control_data_header_size_bits > 0) {