From: Chao Song Date: Mon, 15 May 2023 08:13:01 +0000 (+0800) Subject: soundwire: intel: read AC timing control register before updating it X-Git-Tag: v6.6.7~2420^2~21 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3d912d1a28da59a95e046feff3ea2bc38e00138e;p=platform%2Fkernel%2Flinux-starfive.git soundwire: intel: read AC timing control register before updating it Start from ACE1.x, DOAISE is added to AC timing control register bit 5, it combines with DOAIS to get effective timing, and has the default value 1. The current code fills DOAIS, DACTQE and DODS bits to a variable initialized to zero, and updates the variable to AC timing control register. With this operation, We change DOAISE to 0, and force a much more aggressive timing. The timing is even unable to form a working waveform on SDA pin on Meteorlake. This patch uses read-modify-write operation for the AC timing control register access, thus makes sure those bits not supposed and intended to change are not touched. Signed-off-by: Chao Song Reviewed-by: Pierre-Louis Bossart Reviewed-by: Rander Wang Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20230515081301.12921-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul --- diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index f52167a..26d8485 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -260,7 +260,7 @@ static void intel_shim_init(struct sdw_intel *sdw) { void __iomem *shim = sdw->link_res->shim; unsigned int link_id = sdw->instance; - u16 ioctl = 0, act = 0; + u16 ioctl = 0, act; /* Initialize Shim */ ioctl |= SDW_SHIM_IOCTL_BKE; @@ -281,6 +281,7 @@ static void intel_shim_init(struct sdw_intel *sdw) intel_shim_glue_to_master_ip(sdw); + act = intel_readw(shim, SDW_SHIM_CTMCTL(link_id)); u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); act |= SDW_SHIM_CTMCTL_DACTQE; act |= SDW_SHIM_CTMCTL_DODS;