From: Richard Earnshaw Date: Thu, 15 Dec 2016 15:52:42 +0000 (+0000) Subject: [arm] Eliminate vfp_reg_type X-Git-Tag: upstream/12.2.0~42464 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3d7f68c6d99dedb9c00f7fc97156815bf6acaf50;p=platform%2Fupstream%2Fgcc.git [arm] Eliminate vfp_reg_type Remove the VFP_REGS field by converting its meanings into flag attributes. The new flag attributes build on each other describing increasing capabilities. This allows us to do a better job when inlining functions with differing requiremetns on the fpu environment: we can now inline A into B if B has at least the same register set properties as B (previously we required identical register set properties). * arm.h (vfp_reg_type): Delete. (TARGET_FPU_REGS): Delete. (arm_fpu_desc): Delete regs field. (FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned values. (FPU_FL_DBL, FPU_FL_D32): Define. (TARGET_VFPD32): Use feature test. (TARGET_VFP_SINGLE): Likewise. (TARGET_VFP_DOUBLE): Likewise. * arm-fpus.def: Update all entries for new feature bits. * arm.c (all_fpus): Update initializer macro. (arm_can_inline_p): Remove test on fpu regs. From-SVN: r243707 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6e55f72..4e6be41 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,20 @@ 2016-12-15 Richard Earnshaw + * arm.h (vfp_reg_type): Delete. + (TARGET_FPU_REGS): Delete. + (arm_fpu_desc): Delete regs field. + (FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned + values. + (FPU_FL_DBL, FPU_FL_D32): Define. + (TARGET_VFPD32): Use feature test. + (TARGET_VFP_SINGLE): Likewise. + (TARGET_VFP_DOUBLE): Likewise. + * arm-fpus.def: Update all entries for new feature bits. + * arm.c (all_fpus): Update initializer macro. + (arm_can_inline_p): Remove test on fpu regs. + +2016-12-15 Richard Earnshaw + * arm.h (arm_fp_model): Delete. 2016-12-15 Richard Earnshaw diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index 04b2ef1..eca03bb 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,31 +19,31 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, REV, VFP_REGS, FEATURES) + ARM_FPU(NAME, REV, FEATURES) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", 2, VFP_REG_D16, FPU_FL_NONE) -ARM_FPU("vfpv2", 2, VFP_REG_D16, FPU_FL_NONE) -ARM_FPU("vfpv3", 3, VFP_REG_D32, FPU_FL_NONE) -ARM_FPU("vfpv3-fp16", 3, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("vfpv3-d16", 3, VFP_REG_D16, FPU_FL_NONE) -ARM_FPU("vfpv3-d16-fp16", 3, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("vfpv3xd", 3, VFP_REG_SINGLE, FPU_FL_NONE) -ARM_FPU("vfpv3xd-fp16", 3, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("neon", 3, VFP_REG_D32, FPU_FL_NEON) -ARM_FPU("neon-vfpv3", 3, VFP_REG_D32, FPU_FL_NEON) -ARM_FPU("neon-fp16", 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("vfpv4", 4, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("vfpv4-d16", 4, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("fpv4-sp-d16", 4, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("fpv5-sp-d16", 5, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("fpv5-d16", 5, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("neon-vfpv4", 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("fp-armv8", 8, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("crypto-neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) +ARM_FPU("vfp", 2, FPU_FL_DBL) +ARM_FPU("vfpv2", 2, FPU_FL_DBL) +ARM_FPU("vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL) +ARM_FPU("vfpv3-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("vfpv3-d16", 3, FPU_FL_DBL) +ARM_FPU("vfpv3-d16-fp16", 3, FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("vfpv3xd", 3, FPU_FL_NONE) +ARM_FPU("vfpv3xd-fp16", 3, FPU_FL_FP16) +ARM_FPU("neon", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON) +ARM_FPU("neon-vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON) +ARM_FPU("neon-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("vfpv4-d16", 4, FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("fpv4-sp-d16", 4, FPU_FL_FP16) +ARM_FPU("fpv5-sp-d16", 5, FPU_FL_FP16) +ARM_FPU("fpv5-d16", 5, FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("neon-vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) +ARM_FPU("neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("crypto-neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) /* Compatibility aliases. */ -ARM_FPU("vfp3", 3, VFP_REG_D32, FPU_FL_NONE) +ARM_FPU("vfp3", 3, FPU_FL_D32 | FPU_FL_DBL) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 822ef14..820a6ab 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, REV, VFP_REGS, FEATURES) \ - { NAME, REV, VFP_REGS, FEATURES }, +#define ARM_FPU(NAME, REV, FEATURES) \ + { NAME, REV, FEATURES }, #include "arm-fpus.def" #undef ARM_FPU }; @@ -30218,10 +30218,6 @@ arm_can_inline_p (tree caller, tree callee) if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features) return false; - /* Need same FPU regs. */ - if (callee_fpu->regs != callee_fpu->regs) - return false; - /* OK to inline between different modes. Function with mode specific instructions, e.g using asm, must be explicitly protected with noinline. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 7690e70..a412fb1 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -161,7 +161,7 @@ extern tree arm_fp16_type_node; to be more careful with TARGET_NEON as noted below. */ /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ -#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32) +#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32) /* FPU supports VFPv3 instructions. */ #define TARGET_VFP3 (TARGET_FPU_REV >= 3) @@ -170,10 +170,10 @@ extern tree arm_fp16_type_node; #define TARGET_VFP5 (TARGET_FPU_REV >= 5) /* FPU only supports VFP single-precision instructions. */ -#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE) +#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0) /* FPU supports VFP double-precision instructions. */ -#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE) +#define TARGET_VFP_DOUBLE (TARGET_FPU_FEATURES & FPU_FL_DBL) /* FPU supports half-precision floating-point with NEON element load/store. */ #define TARGET_NEON_FP16 \ @@ -335,24 +335,17 @@ typedef unsigned long arm_fpu_feature_set; #define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F)) /* FPU Features. */ -#define FPU_FL_NONE (0) -#define FPU_FL_NEON (1 << 0) /* NEON instructions. */ -#define FPU_FL_FP16 (1 << 1) /* Half-precision. */ -#define FPU_FL_CRYPTO (1 << 2) /* Crypto extensions. */ - -enum vfp_reg_type -{ - VFP_NONE = 0, - VFP_REG_D16, - VFP_REG_D32, - VFP_REG_SINGLE -}; +#define FPU_FL_NONE (0u) +#define FPU_FL_NEON (1u << 0) /* NEON instructions. */ +#define FPU_FL_FP16 (1u << 1) /* Half-precision. */ +#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */ +#define FPU_FL_DBL (1u << 3) /* Has double precision. */ +#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */ extern const struct arm_fpu_desc { const char *name; int rev; - enum vfp_reg_type regs; arm_fpu_feature_set features; } all_fpus[]; @@ -360,7 +353,6 @@ extern const struct arm_fpu_desc #define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name) #define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev) -#define TARGET_FPU_REGS (all_fpus[arm_fpu_index].regs) #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features) /* Which floating point hardware to schedule for. */