From: Michal Wilczynski Date: Wed, 22 May 2024 16:08:28 +0000 (+0200) Subject: riscv: dts: thead: Add device tree for hdmi port and dependent nodes X-Git-Tag: accepted/tizen/unified/x/20240530.042952~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3d4c1a5f3f7e0a0fc85b0a3ba3be2a666d84db07;p=platform%2Fkernel%2Flinux-thead.git riscv: dts: thead: Add device tree for hdmi port and dependent nodes Hdmi port device tree node requires a lot of extra dependencies. hdmi_tx node depends on disp1_out, which depends on enc1_in. Additionally the main node for display subsystem, called display-subsystem depends on dpu_disp0 and dpu_disp1. There are additional dependencies on dsi0 nodes for lcd0_backlight, pcal6408ahk_d, soc_vdd18_lcd0_en_reg, soc_vdd33_lcd0_en_reg, which in turn brings a lot of pinctrl and i2c nodes. Add all the required nodes for the drm subsystem to load correctly. Ported from vendor kernel [1]. [1] https://gitee.com/thead-yocto/kernel.git Change-Id: Ib2f8daca209caaac175e12d7ea45326b7e3465f0 Signed-off-by: Michal Wilczynski --- diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1675e5db0b3c..9507df3ea7c7 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -17,6 +17,324 @@ device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; }; + + pwm: pwm@ffec01c000 { + compatible = "thead,pwm-light"; + reg = <0xff 0xec01c000 0x0 0x4000>; + #pwm-cells = <2>; + clocks = <&clk CLKGEN_PWM_PCLK>, + <&clk CLKGEN_PWM_CCLK>; + clock-names = "pclk", "cclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; + }; + + display-subsystem { + status = "okay"; + }; + + lcd0_backlight: pwm-backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + aon: aon { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + soc_aud_3v3_en_reg: soc_aud_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + }; + + soc_aud_1v8_en_reg: soc_aud_1v8_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_1v8_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + soc_vdd_3v3_en_reg: soc_vdd_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&porta 30 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vdd33_lcd0_en_reg: soc_lcd0_vdd33_en { + compatible = "regulator-fixed"; + regulator-name = "soc_lcd0_vdd33_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6408ahk_d 5 1>; + enable-active-high; + }; + + soc_vdd18_lcd0_en_reg: soc_lcd0_vdd18_en { + compatible = "regulator-fixed"; + regulator-name = "soc_lcd0_vdd18_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_d 6 1>; + enable-active-high; + }; + + soc_vdd5v_se_en_reg: soc_vdd5v_se_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd5v_se_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portc 14 1>; + enable-active-high; + regulator-always-on; + }; + + soc_wcn33_en_reg: soc_wcn33_en { + compatible = "regulator-fixed"; + regulator-name = "soc_wcn33_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portc 29 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vbus_en_reg: soc_vbus_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vbus_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portb 22 1>; + enable-active-high; + + }; + + soc_avdd28_rgb_reg: soc_avdd28_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 1 1>; + enable-active-high; + }; + + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 2 1>; + enable-active-high; + }; + + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 0 1>; + enable-active-high; + }; + + soc_avdd25_ir_reg: soc_avdd25_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + gpio = <&pcal6408ahk_b 5 1>; + enable-active-high; + }; + + soc_dovdd18_ir_reg: soc_dovdd18_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_b 3 1>; + enable-active-high; + }; + + soc_dvdd12_ir_reg: soc_dvdd12_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pcal6408ahk_b 4 1>; + enable-active-high; + }; + + soc_cam2_avdd25_ir_reg: soc_cam2_avdd25_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_avdd25_ir"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + gpio = <&pcal6408ahk_b 7 1>; + enable-active-high; + }; + + soc_cam2_dovdd18_ir_reg: soc_cam2_dovdd18_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_dovdd18_ir"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_b 6 1>; + enable-active-high; + }; + + soc_cam2_dvdd12_ir_reg: soc_cam2_dvdd12_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_dvdd12_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pcal6408ahk_c 0 1>; + enable-active-high; + }; + + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; }; &padctrl1_apsys { diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 92625cf7d8a2..7eb123bdc2b9 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -16,6 +16,11 @@ gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -33,6 +38,138 @@ status = "okay"; }; +&dpu { + status = "okay"; +}; + +&dpu_enc0 { + status = "disabled"; + + ports { + /* output */ + port@1 { + reg = <1>; + + enc0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; +}; + +&dsi0 { + status = "disabled"; +}; + +&dhost_0 { + panel0@0 { + compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&lcd0_backlight>; + reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */ + hsvcc-supply = <&soc_vdd18_lcd0_en_reg>; + vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_in: endpoint { + remote-endpoint = <&enc0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + + pcal6408ahk_b: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + pcal6408ahk_c: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + + pcal6408ahk_d: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; +}; + &gmac0 { phy-mode = "rgmii-id"; rx-clk-delay = <0x00>; /* for RGMII */ diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8c96f8994ace..decf16d3a7c7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include / { compatible = "thead,th1520"; @@ -149,6 +152,60 @@ #clock-cells = <0>; }; + display-subsystem { + compatible = "verisilicon,display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + status = "disabled"; + }; + + dpu-encoders { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dpu_enc0: dpu-encoder@0 { + /* default encoder is DSI */ + compatible = "verisilicon,dsi-encoder"; + reg = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input */ + port@0 { + reg = <0>; + + enc0_in: endpoint { + remote-endpoint = <&disp0_out>; + }; + }; + }; + }; + + dpu_enc1: dpu-encoder@1 { + /* default encoder is DSI */ + compatible = "verisilicon,dsi-encoder"; + reg = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input */ + port@0 { + reg = <0>; + + enc1_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; + }; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -175,6 +232,86 @@ #address-cells = <1>; #size-cells = <0>; + dummy_clock_apb: apb-clock@0 { + compatible = "fixed-clock"; + reg = <0>; /* Not address, just for index */ + clock-frequency = <62500000>; + clock-output-names = "dummy_clock_apb"; + #clock-cells = <0>; + }; + + dummy_clock_ref: ref-clock@1 { + compatible = "fixed-clock"; + reg = <1>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_ref"; + #clock-cells = <0>; + }; + + dummy_clock_suspend: suspend-clock@2 { + compatible = "fixed-clock"; + reg = <2>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_suspend"; + #clock-cells = <0>; + }; + + dummy_clock_rtc: rtc-clock@3 { + compatible = "fixed-clock"; + reg = <3>; /* Not address, just for index */ + clock-frequency = <32768>; + clock-output-names = "dummy_clock_rtc"; + #clock-cells = <0>; + }; + + dummy_clock_ahb: ahb-clock@4 { + compatible = "fixed-clock"; + reg = <4>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_ahb"; + #clock-cells = <0>; + }; + + dummy_clock_gpu: gpu-clock@6 { + compatible = "fixed-clock"; + reg = <6>; /* Not address, just for index */ + clock-frequency = <18000000>; + clock-output-names = "dummy_clock_gpu"; + #clock-cells = <0>; + }; + + dummy_clock_dphy_ref: dphy-ref-clock@7 { + compatible = "fixed-clock"; + reg = <7>; /* Not address, just for index */ + clock-frequency = <24000000>; + clock-output-names = "dummy_clock_dphy_ref"; + #clock-cells = <0>; + }; + + dummy_clock_dphy_cfg: dphy-cfg-clock@8 { + compatible = "fixed-clock"; + reg = <8>; /* Not address, just for index */ + clock-frequency = <24000000>; + clock-output-names = "dummy_clock_dphy_cfg"; + #clock-cells = <0>; + }; + + dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { + compatible = "fixed-clock"; + reg = <9>; + clock-frequency = <72000000>; + clock-output-names = "dummy_clock_dpu_pixel0"; + #clock-cells = <0>; + }; + + dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { + compatible = "fixed-clock"; + reg = <10>; + clock-frequency = <74250000>; + clock-output-names = "dummy_clock_dpu_pixel1"; + #clock-cells = <0>; + }; + osc_32k: clock-osc-32k@11 { compatible = "fixed-clock"; reg = <11>; @@ -183,6 +320,14 @@ clock-output-names = "osc_32k"; }; + osc_24m: clock-osc-24m@12 { + compatible = "fixed-clock"; + reg = <12>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + rc_24m: clock-rc-24m@13 { compatible = "fixed-clock"; reg = <13>; @@ -191,6 +336,76 @@ clock-output-names = "rc_24m"; }; + dummy_clock_eip: eip-clock@14 { + compatible = "fixed-clock"; + reg = <14>; /* Not address, just for index */ + clock-frequency = <400000000>; + clock-output-names = "dummy_clock_eip"; + #clock-cells = <0>; + }; + + dummy_clock_spi: spi-clock@15 { + compatible = "fixed-clock"; + reg = <15>; /* Not address, just for index */ + clock-frequency = <396000000>; + clock-output-names = "dummy_clock_spi"; + #clock-cells = <0>; + }; + + dummy_clock_qspi: spi-clock@16 { + compatible = "fixed-clock"; + reg = <15>; /* Not address, just for index */ + clock-frequency = <792000000>; + clock-output-names = "dummy_clock_qspi"; + #clock-cells = <0>; + }; + + dummy_gmac_ahb: gmac-ahb-clock@16 { + compatible = "fixed-clock"; + reg = <16>; + clock-frequency = <250000000>; + clock-output-names = "dummy_gmac_ahb"; + #clock-cells = <0>; + }; + + dummy_clock_gmac: gmac-clock@17 { + compatible = "fixed-clock"; + reg = <17>; + clock-frequency = <500000000>; + clock-output-names = "dummy_clock_gmac"; + #clock-cells = <0>; + }; + + dummy_clock_sdhci: sdhci-clock@18 { + compatible = "fixed-clock"; + reg = <18>; /* Not address, just for index */ + clock-frequency = <198000000>; + clock-output-names = "dummy_clock_sdhci"; + #clock-cells = <0>; + }; + + dummy_clock_aonsys_clk: aonsys-clk-clock@19 { + compatible = "fixed-clock"; + reg = <19>; /* Not address, just for index */ + clock-frequency = <73728000>; + clock-output-names = "dummy_clock_aonsys_clk"; + #clock-cells = <0>; + }; + + dummy_clock_uart_sclk: uart-sclk-clock@20 { + compatible = "fixed-clock"; + reg = <20>; /* Not address, just for index */ + clock-frequency = <100000000>; + clock-output-names = "dummy_clock_uart_sclk"; + #clock-cells = <0>; + }; + + dummy_clock_visys: visys-dummy-clock@21 { + compatible = "fixed-clock"; + reg = <21>; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; }; clint: timer@ffdc000000 { @@ -537,6 +752,285 @@ }; }; + mbox_910t: mbox@ffffc38000 { + compatible = "thead,light-mbox"; + reg = <0xff 0xffc38000 0x0 0x4000>, + <0xff 0xffc44000 0x0 0x1000>, + <0xff 0xffc4c000 0x0 0x1000>, + <0xff 0xffc54000 0x0 0x1000>; + reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; + interrupt-parent = <&plic>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dummy_clock_apb>; + clock-names = "ipg"; + icu_cpu_id = <0>; + #mbox-cells = <2>; + }; + + i2c0: i2c@ffe7f20000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLKGEN_I2C0_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@ffe7f24000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLKGEN_I2C1_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@ffec00c000{ + compatible = "snps,designware-i2c"; + reg = <0xff 0xec00c000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLKGEN_I2C2_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + + i2c3: i2c@ffec014000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLKGEN_I2C3_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 18>, <&dmac0 19>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@ffe7f28000{ + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLKGEN_I2C4_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi0: dw-mipi-dsi0@ffef500000 { + compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; + reg = <0xff 0xef500000 0x0 0x10000>; + status = "disabled"; + + dphy_0: dsi0-dphy { + compatible = "thead,light-mipi-dphy"; + regmap = <&dsi0>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, + <&clk OSC_24M>, + <&clk OSC_24M>; + clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; + #phy-cells = <0>; + }; + + dhost_0: dsi0-host { + compatible = "verisilicon,dw-mipi-dsi"; + regmap = <&dsi0>; + interrupt-parent = <&plic>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>; + clock-names = "pclk", "pixclk"; + phys = <&dphy_0>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dsi1: dw-mipi-dsi1@ffef510000 { + compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; + reg = <0xff 0xef510000 0x0 0x10000>; + status = "disabled"; + + dphy_1: dsi1-dphy { + compatible = "thead,light-mipi-dphy"; + regmap = <&dsi1>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, + <&clk OSC_24M>, + <&clk OSC_24M>; + clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; + #phy-cells = <0>; + }; + + dhost_1: dsi1-host { + compatible = "verisilicon,dw-mipi-dsi"; + regmap = <&dsi1>; + interrupt-parent = <&plic>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>; + clock-names = "pclk", "pixclk"; + phys = <&dphy_1>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */ + compatible = "thead,vosys-gate-controller"; + reg = <0xff 0xef528000 0x0 0x1000>; + #clock-cells = <1>; + status = "okay"; + }; + + dpu: dc8200@ffef600000 { + compatible = "verisilicon,dc8200"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff 0xef600000 0x0 0x100>, + <0xff 0xef600800 0x0 0x2000>, + <0xff 0xef630010 0x0 0x60>; + interrupt-parent = <&plic>; + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>, + <&clk DPU0_PLL_DIV_CLK>, + <&clk DPU1_PLL_DIV_CLK>, + <&clk DPU0_PLL_FOUTPOSTDIV>, + <&clk DPU1_PLL_FOUTPOSTDIV>; + clock-names = "core_clk", "pix_clk0", "pix_clk1", + "axi_clk", "cfg_clk", "pixclk0", + "pixclk1", "dpu0_pll_foutpostdiv", + "dpu1_pll_foutpostdiv"; + status = "disabled"; + + dpu_disp0: port@0 { + reg = <0>; + + disp0_out: endpoint { + remote-endpoint = <&enc0_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + disp1_out: endpoint { + remote-endpoint = <&enc1_in>; + }; + }; + }; + + vosys_reg: vosys@ffef528000 { + compatible = "thead,light-vo-subsys", "syscon"; + reg = <0xff 0xef528000 0x0 0x1000>; + status = "okay"; + }; + + hdmi_tx: dw-hdmi-tx@ffef540000 { + compatible = "thead,light-hdmi-tx"; + reg = <0xff 0xef540000 0x0 0x40000>; + interrupt-parent = <&plic>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>; + clock-names = "iahb", "isfr", "cec", "pixclk"; + reg-io-width = <4>; + phy_version = <301>; + /* TODO: add phy property */ + status = "disabled"; + }; + stmmac_axi_setup: stmmac-axi-config { snps,wr_osr_lmt = <3>; snps,rd_osr_lmt = <3>;