From: Marek Olšák Date: Tue, 19 May 2020 03:14:03 +0000 (-0400) Subject: radeonsi: don't use INDIRECT_BUFFER within IBs X-Git-Tag: upstream/21.0.0~9534 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3cd96b510938536e264907aa3886774a853c0821;p=platform%2Fupstream%2Fmesa.git radeonsi: don't use INDIRECT_BUFFER within IBs It's fragile. If I change the size or alignment, it hangs. Better safe than sorry. Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 9b63ba6..00db2ff 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -147,34 +147,3 @@ void si_pm4_reset_emitted(struct si_context *sctx) memset(&sctx->emitted, 0, sizeof(sctx->emitted)); sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES); } - -void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state) -{ - struct pipe_screen *screen = sctx->b.screen; - unsigned aligned_ndw = align(state->ndw, 8); - - /* only supported on GFX7 and later */ - if (sctx->chip_class < GFX7) - return; - - assert(state->ndw); - assert(aligned_ndw <= SI_PM4_MAX_DW); - - si_resource_reference(&state->indirect_buffer, NULL); - /* TODO: this hangs with 1024 or higher alignment on GFX9. */ - state->indirect_buffer = - si_aligned_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, aligned_ndw * 4, 256); - if (!state->indirect_buffer) - return; - - /* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */ - if (sctx->screen->info.gfx_ib_pad_with_type2) { - for (int i = state->ndw; i < aligned_ndw; i++) - state->pm4[i] = 0x80000000; /* type2 nop packet */ - } else { - for (int i = state->ndw; i < aligned_ndw; i++) - state->pm4[i] = 0xffff1000; /* type3 nop packet */ - } - - pipe_buffer_write(&sctx->b, &state->indirect_buffer->b.b, 0, aligned_ndw * 4, state->pm4); -} diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index 783833e..cde42ba 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -71,7 +71,6 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate); void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage, enum radeon_bo_priority priority); -void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state); void si_pm4_clear_state(struct si_pm4_state *state); void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 9ae618c..75f439b 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5415,6 +5415,5 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0); } - si_pm4_upload_indirect_buffer(sctx, pm4); sctx->init_config = pm4; } diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 4f37852..759353c 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -3396,7 +3396,6 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) if (!sctx->init_config_has_vgt_flush) { si_init_config_add_vgt_flush(sctx); - si_pm4_upload_indirect_buffer(sctx, sctx->init_config); } /* Flush the context to re-emit both init_config states. */ @@ -3663,7 +3662,6 @@ static void si_init_tess_factor_ring(struct si_context *sctx) /* Flush the context to re-emit the init_config state. * This is done only once in a lifetime of a context. */ - si_pm4_upload_indirect_buffer(sctx, sctx->init_config); sctx->initial_gfx_cs_size = 0; /* force flush */ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); }