From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun, 5 Dec 2010 16:45:02 +0000 (+0000)
Subject: drm/i915: Power Context register is only available for gen4 mobiles
X-Git-Tag: upstream/snapshot3+hdmi~12084^2~23^2~33
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3c8cdf9b60b98c5b408e2cfbcab3160e25e5af5a;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

drm/i915: Power Context register is only available for gen4 mobiles

The ability to save the hardware context upon powering down the render
clock through PWRCTXA is only available on a couple of gen4 chipsets.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a95c693..aba1c33 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5973,7 +5973,7 @@ void intel_init_clock_gating(struct drm_device *dev)
 				       "Disable RC6\n");
 	}
 
-	if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
+	if (IS_GEN4(dev) && IS_MOBILE(dev)) {
 		if (dev_priv->pwrctx == NULL)
 			dev_priv->pwrctx = intel_alloc_context_page(dev);
 		if (dev_priv->pwrctx) {