From: Simon Glass <sjg@chromium.org>
Date: Sun, 30 Aug 2015 22:55:33 +0000 (-0600)
Subject: rockchip: rk3288: Add SoC reset driver
X-Git-Tag: v2015.10-rc3~6^2~19
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3c5d0e34f6fe64144de0ad84e42f113c1cc2e0ca;p=platform%2Fkernel%2Fu-boot.git

rockchip: rk3288: Add SoC reset driver

We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile
new file mode 100644
index 0000000..c6663f0
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015 Google, Inc
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += reset_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
new file mode 100644
index 0000000..7affd11
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+{
+	struct rk3288_cru *cru = rockchip_get_cru();
+
+	if (IS_ERR(cru))
+		return PTR_ERR(cru);
+	switch (type) {
+	case RESET_WARM:
+		writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
+		writel(0xeca8, &cru->cru_glb_srst_snd_value);
+		break;
+	case RESET_COLD:
+		writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
+		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct reset_ops rk3288_reset = {
+	.request	= rk3288_reset_request,
+};
+
+U_BOOT_DRIVER(reset_rk3288) = {
+	.name	= "rk3288_reset",
+	.id	= UCLASS_RESET,
+	.ops	= &rk3288_reset,
+};