From: Peter Ujfalusi Date: Wed, 26 May 2010 08:38:19 +0000 (+0300) Subject: ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default X-Git-Tag: v3.0~832^2~32^2~721^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3c36cc688e7ad4ab595a0ac59697e4e1d06338c5;p=platform%2Fkernel%2Flinux-amlogic.git ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default It seams at least on twl5031 that the ARXR2_APGA_CTL register does not have the same default value as it is written in the TRM. Since the codec part of the PM chip has not been actually changed according to TI, assuming, that all version has the same problem, so writing there the TRM value. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 30b7bba..c667ca5a8 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -289,6 +289,9 @@ static void twl4030_init_chip(struct platform_device *pdev) TWL4030_ATXL1_EN | TWL4030_ATXR1_EN | TWL4030_ARXL2_EN | TWL4030_ARXR2_EN); + /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */ + twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32); + /* Machine dependent setup */ if (!setup) return;