From: Pat Gavlin <pgavlin@gmail.com>
Date: Thu, 17 Nov 2016 16:47:27 +0000 (-0800)
Subject: Address PR feedback.
X-Git-Tag: submit/tizen/20210909.063632~11030^2~8858^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3c1256880c353feef1ab63afd012562363c2c33f;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

Address PR feedback.


Commit migrated from https://github.com/dotnet/coreclr/commit/c30cd2b84608cc855cf0603c268fb126665b42a4
---

diff --git a/src/coreclr/src/jit/emitxarch.cpp b/src/coreclr/src/jit/emitxarch.cpp
index f9fd898..7c384aa 100644
--- a/src/coreclr/src/jit/emitxarch.cpp
+++ b/src/coreclr/src/jit/emitxarch.cpp
@@ -2903,10 +2903,18 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
         varNum = tmpDsc->tdTempNum();
         offset = 0;
     }
-    else if (memBase->OperGet() == GT_LCL_VAR_ADDR)
+    else
     {
-        varNum = memBase->AsLclVarCommon()->GetLclNum();
-        offset = 0;
+        // At this point we must have a memory operand that is a contained indir: if we do not, we should have handled
+        // this instruction above in the reg/imm or reg/reg case.
+        assert(mem != nullptr);
+        assert(memBase != nullptr);
+
+        if (memBase->OperGet() == GT_LCL_VAR_ADDR)
+        {
+            varNum = memBase->AsLclVarCommon()->GetLclNum();
+            offset = 0;
+        }
     }
 
     // Spill temp numbers are negative and start with -1
@@ -2915,8 +2923,7 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
     if (varNum != BAD_VAR_NUM || tmpDsc != nullptr)
     {
         // Is the memory op in the source position?
-        if (src->isContainedLclField() || src->isContainedLclVar() || src->isContainedSpillTemp() ||
-            src->isContainedMemoryOp())
+        if (src->isContainedMemoryOp())
         {
             if (instrHasImplicitRegPairDest(ins))
             {