From: Peikang Zhang <peikang.zhang@amd.com>
Date: Mon, 8 Jun 2020 18:28:35 +0000 (-0400)
Subject: drm/amd/display: Red screen observed on startup
X-Git-Tag: v5.10.7~1861^2~25^2~20
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3c08d625d6c456fa34dd32e2ae14911ccdfa8c85;p=platform%2Fkernel%2Flinux-rpi.git

drm/amd/display: Red screen observed on startup

[Why]
We try to to change new_clocks->dppclk_khz to 100000 when
new_clocks->dppclk_khz is 0

[How]
Don't change new_clocks->dppclk_khz value when new_clocks->dppclk_khz is
0

Signed-off-by: Peikang Zhang <peikang.zhang@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 24c57658..39788a7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -153,8 +153,9 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 
 	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
+	// Do not adjust dppclk if dppclk is 0 to avoid unexpected result
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
-		if (new_clocks->dppclk_khz < 100000)
+		if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
 			new_clocks->dppclk_khz = 100000;
 	}