From: Carlos Xiong <clever.xiong@amd.com>
Date: Mon, 15 Dec 2014 03:50:15 +0000 (-0500)
Subject: amdgpu/addrlib: force all zero tile info for linear general.
X-Git-Tag: upstream/17.1.0~881
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3bd1380ab2aea14d6187110982b8ba576eefb073;p=platform%2Fupstream%2Fmesa.git

amdgpu/addrlib: force all zero tile info for linear general.
---

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index f72f5a2..d4f8c64 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -555,7 +555,16 @@ ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg(
     // Global flag to control usage of tileIndex
     if (UseTileIndex(index))
     {
-        if (static_cast<UINT_32>(index) >= m_noOfEntries)
+        if (index == TileIndexLinearGeneral)
+        {
+            pInfo->banks = 2;
+            pInfo->bankWidth = 1;
+            pInfo->bankHeight = 1;
+            pInfo->macroAspectRatio = 1;
+            pInfo->tileSplitBytes = 64;
+            pInfo->pipeConfig = ADDR_PIPECFG_P2;
+        }
+        else if (static_cast<UINT_32>(index) >= m_noOfEntries)
         {
             returnCode = ADDR_INVALIDPARAMS;
         }