From: Eric Anholt Date: Fri, 27 Mar 2009 20:13:47 +0000 (-0700) Subject: intel_gpu_top: Add more 965 bits. X-Git-Tag: 1.0~25 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ba49a9295370cbcbb3139674556ea723c1a6b6c;p=profile%2Fextras%2Fintel-gpu-tools.git intel_gpu_top: Add more 965 bits. --- diff --git a/i810_reg.h b/i810_reg.h index bc462fa..2b7492a 100644 --- a/i810_reg.h +++ b/i810_reg.h @@ -404,16 +404,34 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define IPEIR_I965 0x2064 /* i965 */ #define IPEHR_I965 0x2068 /* i965 */ #define INST_DONE_I965 0x206c +# define I965_ROW_0_EU_0_DONE (1 << 31) +# define I965_ROW_0_EU_1_DONE (1 << 30) +# define I965_ROW_0_EU_2_DONE (1 << 29) +# define I965_ROW_0_EU_3_DONE (1 << 28) +# define I965_ROW_1_EU_0_DONE (1 << 27) +# define I965_ROW_1_EU_1_DONE (1 << 26) +# define I965_ROW_1_EU_2_DONE (1 << 25) +# define I965_ROW_1_EU_3_DONE (1 << 24) # define I965_SF_DONE (1 << 23) # define I965_SE_DONE (1 << 22) # define I965_WM_DONE (1 << 21) +# define I965_DISPATCHER_DONE (1 << 18) +# define I965_PROJECTION_DONE (1 << 17) +# define I965_DG_DONE (1 << 16) +# define I965_QUAD_CACHE_DONE (1 << 15) # define I965_TEXTURE_FETCH_DONE (1 << 14) +# define I965_TEXTURE_DECOMPRESS_DONE (1 << 13) # define I965_SAMPLER_CACHE_DONE (1 << 12) # define I965_FILTER_DONE (1 << 11) +# define I965_BYPASS_DONE (1 << 10) # define I965_PS_DONE (1 << 9) # define I965_CC_DONE (1 << 8) # define I965_MAP_FILTER_DONE (1 << 7) # define I965_MAP_L2_IDLE (1 << 6) +# define I965_MA_ROW_0_DONE (1 << 5) +# define I965_MA_ROW_1_DONE (1 << 4) +# define I965_IC_ROW_0_DONE (1 << 3) +# define I965_IC_ROW_1_DONE (1 << 2) # define I965_CP_DONE (1 << 1) # define I965_RING_0_ENABLE (1 << 0) #define INST_PS_I965 0x2070 diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index 9e4ae6b..c08b7a8 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -88,17 +88,35 @@ int main(int argc, char **argv) intel_get_mmio(); if (IS_965(devid)) { - add_instdone_bit(I965_SF_DONE, "Perspective interpolation"); - add_instdone_bit(I965_SE_DONE, "Dispatcher"); - add_instdone_bit(I965_WM_DONE, "Projection and LOD"); + add_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0"); + add_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1"); + add_instdone_bit(I965_ROW_0_EU_2_DONE, "Row 0, EU 2"); + add_instdone_bit(I965_ROW_0_EU_3_DONE, "Row 0, EU 3"); + add_instdone_bit(I965_ROW_1_EU_0_DONE, "Row 1, EU 0"); + add_instdone_bit(I965_ROW_1_EU_1_DONE, "Row 1, EU 1"); + add_instdone_bit(I965_ROW_1_EU_2_DONE, "Row 1, EU 2"); + add_instdone_bit(I965_ROW_1_EU_3_DONE, "Row 1, EU 3"); + add_instdone_bit(I965_SF_DONE, "Strips and Fans"); + add_instdone_bit(I965_SE_DONE, "Setup Engine"); + add_instdone_bit(I965_WM_DONE, "Windowizer"); + add_instdone_bit(I965_DISPATCHER_DONE, "Dispatcher"); + add_instdone_bit(I965_PROJECTION_DONE, "Projection and LOD"); + add_instdone_bit(I965_DG_DONE, "Dependent address generator"); + add_instdone_bit(I965_QUAD_CACHE_DONE, "Texture fetch"); add_instdone_bit(I965_TEXTURE_FETCH_DONE, "Texture fetch"); - add_instdone_bit(I965_SAMPLER_CACHE_DONE, "Sampler Cache"); + add_instdone_bit(I965_TEXTURE_DECOMPRESS_DONE, "Texture decompress"); + add_instdone_bit(I965_SAMPLER_CACHE_DONE, "Sampler cache"); add_instdone_bit(I965_FILTER_DONE, "Filtering"); + add_instdone_bit(I965_BYPASS_DONE, "Bypass FIFO"); add_instdone_bit(I965_PS_DONE, "Pixel shader"); add_instdone_bit(I965_CC_DONE, "Color calculator"); add_instdone_bit(I965_MAP_FILTER_DONE, "Map filter"); add_instdone_bit(I965_MAP_L2_IDLE, "Map L2"); - add_instdone_bit(I965_CP_DONE, "CP"); + add_instdone_bit(I965_MA_ROW_0_DONE, "Message Arbiter row 0"); + add_instdone_bit(I965_MA_ROW_1_DONE, "Message Arbiter row 1"); + add_instdone_bit(I965_IC_ROW_0_DONE, "Instruction cache row 0"); + add_instdone_bit(I965_IC_ROW_1_DONE, "Instruction cache row 1"); + add_instdone_bit(I965_CP_DONE, "Command Processor"); } else if (IS_9XX(devid)) { add_instdone_bit(IDCT_DONE, "IDCT"); add_instdone_bit(IQ_DONE, "IQ");