From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Thu, 25 Oct 2012 19:15:47 +0000 (-0700)
Subject: drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
X-Git-Tag: v3.8-rc1~42^2~193^2~25
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ac7831314eba873d60b58718123c503f6961337;p=platform%2Fkernel%2Flinux-exynos.git

drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1591955..f7617a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -245,7 +245,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);