From: Michal Wilczynski Date: Fri, 10 May 2024 11:21:26 +0000 (+0200) Subject: riscv: dts: thead: Add device tree for ethernet and dependent nodes X-Git-Tag: accepted/tizen/unified/x/20240514.123342~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ac77623d76c58bdab61965cfcce8d61a5963baf;p=platform%2Fkernel%2Flinux-thead.git riscv: dts: thead: Add device tree for ethernet and dependent nodes Ethernet support device tree nodes depends on multiple device tree nodes: pinctrl, clocks, nvmem controller for efuse. Add them, so the ethernet node dependencies are satisfied. Ported from vendor kernel [1]. [1] https://gitee.com/thead-yocto/kernel.git Change-Id: Ic44fb31705ec20940df2f4b01c234f2dbfba88be Signed-off-by: Michal Wilczynski --- diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 9a3884a73e13..72521d0895e8 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -4,12 +4,17 @@ */ #include "th1520-lichee-module-4a.dtsi" +#include +#include + / { model = "Sipeed Lichee Pi 4A"; compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -30,3 +35,241 @@ &uart0 { status = "okay"; }; + +&padctrl1_apsys { + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + >; + }; + + pinctrl_i2c0: i2c0grp { + thead,pins = < + FM_I2C0_SCL 0x0 0x204 + FM_I2C0_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c1: i2c1grp { + thead,pins = < + FM_I2C1_SCL 0x0 0x204 + FM_I2C1_SDA 0x0 0x204 + >; + }; + + pinctrl_uart1: uart1grp { + thead,pins = < + FM_UART1_TXD 0x0 0x202 + FM_UART1_RXD 0x0 0x202 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x202 + FM_UART4_RXD 0x0 0x202 + FM_UART4_CTSN 0x0 0x202 + FM_UART4_RTSN 0x0 0x202 + >; + }; + + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x1 0x202 + FM_UART3_RXD 0x1 0x202 + >; + }; + + pinctrl_wifi_wake: wifi_grp { + thead,pins = < + FM_GPIO0_27 0x0 0x202 + >; + }; + + pinctrl_bt_wake: bt_grp { + thead,pins = < + FM_GPIO0_28 0x0 0x202 + >; + }; + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_CLK_OUT_2 0x3 0x208 + >; + }; + }; +}; + +&padctrl0_apsys { + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x202 + FM_UART0_RXD 0x0 0x202 + >; + }; + + pinctrl_i2c2: i2c2grp { + thead,pins = < + FM_I2C2_SCL 0x0 0x204 + FM_I2C2_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c3: i2c3grp { + thead,pins = < + FM_I2C3_SCL 0x0 0x204 + FM_I2C3_SDA 0x0 0x204 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_light_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_gmac1: gmac1grp { + thead,pins = < + FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */ + FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */ + FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */ + FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */ + FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */ + FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */ + FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */ + FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */ + FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */ + FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */ + FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */ + FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */ + >; + }; + + pinctrl_sdio0: sdio0grp { + thead,pins = < + FM_SDIO0_DETN 0x0 0x202 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x20f /* pwm0 */ + FM_GPIO3_3 0x1 0x20f /* pwm1 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + thead,pins = < + FM_HDMI_SCL 0x0 0x202 + FM_HDMI_SDA 0x0 0x202 + FM_HDMI_CEC 0x0 0x202 + >; + }; + + pinctrl_gmac0: gmac0grp { + thead,pins = < + FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ + FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ + FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ + FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ + FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ + FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ + FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ + FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ + FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ + FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ + FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ + FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ + FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ + FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ + FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ + FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ + >; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1>; + +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8b915e206f3a..af5eb6418871 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -5,6 +5,8 @@ */ #include +#include +#include / { compatible = "thead,th1520"; @@ -134,6 +136,14 @@ #clock-cells = <0>; }; + rc_24m: clock-rc-24m@13 { + compatible = "fixed-clock"; + reg = <13>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "rc_24m"; + }; + apb_clk: apb-clk-clock { compatible = "fixed-clock"; clock-output-names = "apb_clk"; @@ -465,5 +475,123 @@ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; }; }; + + miscsys_reg: miscsys-reg@ffec02c000 { + compatible = "thead,light-miscsys-reg", "syscon"; + reg = <0xff 0xec02c000 0x0 0x1000>; + status = "okay"; + }; + + tee_miscsys_reg: tee_miscsys-reg@fffc02d000 { + compatible = "thead,light-miscsys-reg", "syscon"; + reg = <0xff 0xfc02d000 0x0 0x1000>; + status = "okay"; + }; + + clk: clock-controller@ffef010000 { + compatible = "thead,light-fm-ree-clk"; + reg = <0xff 0xef010000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc>, <&rc_24m>; + clock-names = "osc_32k", "osc", "rc_24m"; + status = "okay"; + }; + + miscsys_clk_gate: miscsys-clk-gate { + compatible = "thead,miscsys-gate-controller"; + miscsys-regmap = <&miscsys_reg>; + tee-miscsys-regmap = <&tee_miscsys_reg>; + #clock-cells = <1>; + status = "okay"; + }; + + teesys_syscon: teesys-reg@ffff200000 { + compatible = "syscon"; + reg = <0xff 0xff200000 0x0 0x10000>; + }; + + nvmem_controller: efuse@ffff210000 { + compatible = "thead,light-fm-efuse", "syscon"; + reg = <0xff 0xff210000 0x0 0x10000>; + thead,teesys = <&teesys_syscon>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>; + clock-names = "pclk"; + + gmac0_mac_address: mac-address@176 { + reg = <0xb0 6>; + }; + + gmac1_mac_address: mac-address@184 { + reg = <0xb8 6>; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <3>; + snps,rd_osr_lmt = <3>; + snps,blen = <16 8 4 0 0 0 0>; + }; + + padctrl1_apsys: padctrl1-apsys@ffe7f3c000 { + compatible = "thead,light-fm-left-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>; + clock-names = "pclk"; + status = "okay"; + }; + + padctrl0_apsys: padctrl0-apsys@ffec007000 { + compatible = "thead,light-fm-right-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>; + clock-names = "pclk"; + status = "okay"; + }; + + gmac0: ethernet@ffe7070000 { + compatible = "thead,light-dwmac"; + reg = <0xff 0xe7070000 0x0 0x2000 + 0xff 0xec00301c 0x0 0x4 + 0xff 0xec003020 0x0 0x4 + 0xff 0xec003000 0x0 0x1c>; + reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; + interrupt-parent = <&plic>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLKGEN_GMAC0_CCLK>, + <&clk CLKGEN_GMAC0_PCLK>, + <&clk CLKGEN_GMAC_AXI_ACLK>, + <&clk CLKGEN_GMAC_AXI_PCLK>; + clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,axi-config = <&stmmac_axi_setup>; + nvmem-cells = <&gmac0_mac_address>; + nvmem-cell-names = "mac-address"; + }; + + gmac1: ethernet@ffe7060000 { + compatible = "thead,light-dwmac"; + reg = <0xff 0xe7060000 0x0 0x2000 + 0xff 0xec00401c 0x0 0x4 + 0xff 0xec004020 0x0 0x4 + 0xff 0xec004000 0x0 0x1c>; + reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; + interrupt-parent = <&plic>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLKGEN_GMAC1_CCLK>, + <&clk CLKGEN_GMAC1_PCLK>, + <&clk CLKGEN_GMAC_AXI_ACLK>, + <&clk CLKGEN_GMAC_AXI_PCLK>; + clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,axi-config = <&stmmac_axi_setup>; + nvmem-cells = <&gmac1_mac_address>; + nvmem-cell-names = "mac-address"; + }; }; };