From: Diana Picus <diana.picus@linaro.org>
Date: Mon, 20 Nov 2017 11:05:31 +0000 (+0000)
Subject: [ARM GlobalISel] Add test for RSBri. NFC
X-Git-Tag: llvmorg-6.0.0-rc1~3021
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3ac504035a8c1588f6c333754cbc2d62e9b19847;p=platform%2Fupstream%2Fllvm.git

[ARM GlobalISel] Add test for RSBri. NFC

Add instruction selector test for RSBri, which is derived from
AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is
derived from the very similar AsI1_bin_irs pattern.

llvm-svn: 318643
---

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index d89ddef..122ea77 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -18,6 +18,8 @@
   define void @test_fsub_s64() #0 { ret void }
 
   define void @test_sub_s32() { ret void }
+  define void @test_sub_imm_s32() { ret void }
+  define void @test_sub_rev_imm_s32() { ret void }
 
   define void @test_mul_s32() #1 { ret void }
   define void @test_mulv5_s32() { ret void }
@@ -471,6 +473,62 @@ body:             |
     ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
+name:            test_sub_imm_s32
+# CHECK-LABEL: name: test_sub_imm_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+    %1(s32) = G_CONSTANT i32 17
+    %2(s32) = G_SUB %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _
+
+    %r0 = COPY %2(s32)
+    ; CHECK: %r0 = COPY [[VREGRES]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name:            test_sub_rev_imm_s32
+# CHECK-LABEL: name: test_sub_rev_imm_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+    %1(s32) = G_CONSTANT i32 17
+    %2(s32) = G_SUB %1, %0
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _
+
+    %r0 = COPY %2(s32)
+    ; CHECK: %r0 = COPY [[VREGRES]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
 name:            test_mul_s32
 # CHECK-LABEL: name: test_mul_s32
 legalized:       true