From: Justin Lebar Date: Wed, 7 Sep 2016 15:49:48 +0000 (+0000) Subject: [LSV] Use the original loads' names for the extractelement instructions. X-Git-Tag: llvmorg-4.0.0-rc1~10453 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3a5f40c19175390e3790867972820599060016de;p=platform%2Fupstream%2Fllvm.git [LSV] Use the original loads' names for the extractelement instructions. Summary: LSV replaces multiple adjacent loads with one vectorized load and a bunch of extractelement instructions. This patch makes the extractelement instructions' names match those of the original loads, for (hopefully) improved readability. Reviewers: asbirlea, tstellarAMD Subscribers: arsenm, mzolotukhin Differential Revision: https://reviews.llvm.org/D23748 llvm-svn: 280818 --- diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp index 90adf9f..72a0965 100644 --- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp @@ -983,7 +983,8 @@ bool Vectorizer::vectorizeLoadChain( Instruction *UI = cast(Use); unsigned Idx = cast(UI->getOperand(1))->getZExtValue(); unsigned NewIdx = Idx + I * VecWidth; - Value *V = Builder.CreateExtractElement(LI, Builder.getInt32(NewIdx)); + Value *V = Builder.CreateExtractElement(LI, Builder.getInt32(NewIdx), + UI->getName()); if (V->getType() != UI->getType()) V = Builder.CreateBitCast(V, UI->getType()); @@ -1002,8 +1003,9 @@ bool Vectorizer::vectorizeLoadChain( I->eraseFromParent(); } else { for (unsigned I = 0, E = Chain.size(); I != E; ++I) { - Value *V = Builder.CreateExtractElement(LI, Builder.getInt32(I)); Value *CV = Chain[I]; + Value *V = + Builder.CreateExtractElement(LI, Builder.getInt32(I), CV->getName()); if (V->getType() != CV->getType()) { V = Builder.CreateBitOrPointerCast(V, CV->getType()); } diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll index 03265ef..d32387f 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -196,11 +196,11 @@ define void @merge_global_store_4_constants_i64(i64 addrspace(1)* %out) #0 { } ; CHECK-LABEL: @merge_global_store_2_adjacent_loads_i32 -; CHECK: [[LOAD:%[0-9]+]] = load <2 x i32> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i32> [[LOAD]], i32 0 -; CHECK: [[ELT1:%[0-9]+]] = extractelement <2 x i32> [[LOAD]], i32 1 -; CHECK: [[INSERT0:%[0-9]+]] = insertelement <2 x i32> undef, i32 [[ELT0]], i32 0 -; CHECK: [[INSERT1:%[0-9]+]] = insertelement <2 x i32> [[INSERT0]], i32 [[ELT1]], i32 1 +; CHECK: [[LOAD:%[^ ]+]] = load <2 x i32> +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i32> [[LOAD]], i32 0 +; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i32> [[LOAD]], i32 1 +; CHECK: [[INSERT0:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[ELT0]], i32 0 +; CHECK: [[INSERT1:%[^ ]+]] = insertelement <2 x i32> [[INSERT0]], i32 [[ELT1]], i32 1 ; CHECK: store <2 x i32> [[INSERT1]] define void @merge_global_store_2_adjacent_loads_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1 @@ -235,11 +235,11 @@ define void @merge_global_store_2_adjacent_loads_i32_nonzero_base(i32 addrspace( } ; CHECK-LABEL: @merge_global_store_2_adjacent_loads_shuffle_i32 -; CHECK: [[LOAD:%[0-9]+]] = load <2 x i32> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i32> [[LOAD]], i32 0 -; CHECK: [[ELT1:%[0-9]+]] = extractelement <2 x i32> [[LOAD]], i32 1 -; CHECK: [[INSERT0:%[0-9]+]] = insertelement <2 x i32> undef, i32 [[ELT1]], i32 0 -; CHECK: [[INSERT1:%[0-9]+]] = insertelement <2 x i32> [[INSERT0]], i32 [[ELT0]], i32 1 +; CHECK: [[LOAD:%[^ ]+]] = load <2 x i32> +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i32> [[LOAD]], i32 0 +; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i32> [[LOAD]], i32 1 +; CHECK: [[INSERT0:%[^ ]+]] = insertelement <2 x i32> undef, i32 [[ELT1]], i32 0 +; CHECK: [[INSERT1:%[^ ]+]] = insertelement <2 x i32> [[INSERT0]], i32 [[ELT0]], i32 1 ; CHECK: store <2 x i32> [[INSERT1]] define void @merge_global_store_2_adjacent_loads_shuffle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll index 9b73f34..202e988 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll @@ -6,8 +6,8 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 ; CHECK-LABEL: @merge_v2p1i8( ; CHECK: load <2 x i64> -; CHECK: inttoptr i64 %{{[0-9]+}} to i8 addrspace(1)* -; CHECK: inttoptr i64 %{{[0-9]+}} to i8 addrspace(1)* +; CHECK: inttoptr i64 %{{[^ ]+}} to i8 addrspace(1)* +; CHECK: inttoptr i64 %{{[^ ]+}} to i8 addrspace(1)* ; CHECK: store <2 x i64> zeroinitializer define void @merge_v2p1i8(i8 addrspace(1)* addrspace(1)* nocapture %a, i8 addrspace(1)* addrspace(1)* nocapture readonly %b) #0 { entry: @@ -25,8 +25,8 @@ entry: ; CHECK-LABEL: @merge_v2p3i8( ; CHECK: load <2 x i32> -; CHECK: inttoptr i32 %{{[0-9]+}} to i8 addrspace(3)* -; CHECK: inttoptr i32 %{{[0-9]+}} to i8 addrspace(3)* +; CHECK: inttoptr i32 %{{[^ ]+}} to i8 addrspace(3)* +; CHECK: inttoptr i32 %{{[^ ]+}} to i8 addrspace(3)* ; CHECK: store <2 x i32> zeroinitializer define void @merge_v2p3i8(i8 addrspace(3)* addrspace(3)* nocapture %a, i8 addrspace(3)* addrspace(3)* nocapture readonly %b) #0 { entry: @@ -44,7 +44,7 @@ entry: ; CHECK-LABEL: @merge_load_i64_ptr64( ; CHECK: load <2 x i64> -; CHECK: [[ELT1:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 1 +; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1 ; CHECK: inttoptr i64 [[ELT1]] to i8 addrspace(1)* define void @merge_load_i64_ptr64(i64 addrspace(1)* nocapture %a) #0 { entry: @@ -59,7 +59,7 @@ entry: ; CHECK-LABEL: @merge_load_ptr64_i64( ; CHECK: load <2 x i64> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 0 +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0 ; CHECK: inttoptr i64 [[ELT0]] to i8 addrspace(1)* define void @merge_load_ptr64_i64(i64 addrspace(1)* nocapture %a) #0 { entry: @@ -73,7 +73,7 @@ entry: } ; CHECK-LABEL: @merge_store_ptr64_i64( -; CHECK: [[ELT0:%[0-9]+]] = ptrtoint i8 addrspace(1)* %ptr0 to i64 +; CHECK: [[ELT0:%[^ ]+]] = ptrtoint i8 addrspace(1)* %ptr0 to i64 ; CHECK: insertelement <2 x i64> undef, i64 [[ELT0]], i32 0 ; CHECK: store <2 x i64> define void @merge_store_ptr64_i64(i64 addrspace(1)* nocapture %a, i8 addrspace(1)* %ptr0, i64 %val1) #0 { @@ -89,8 +89,8 @@ entry: } ; CHECK-LABEL: @merge_store_i64_ptr64( -; CHECK: [[ELT1:%[0-9]+]] = ptrtoint i8 addrspace(1)* %ptr1 to i64 -; CHECK: insertelement <2 x i64> %{{[0-9]+}}, i64 [[ELT1]], i32 1 +; CHECK: [[ELT1:%[^ ]+]] = ptrtoint i8 addrspace(1)* %ptr1 to i64 +; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1]], i32 1 ; CHECK: store <2 x i64> define void @merge_store_i64_ptr64(i8 addrspace(1)* addrspace(1)* nocapture %a, i64 %val0, i8 addrspace(1)* %ptr1) #0 { entry: @@ -105,7 +105,7 @@ entry: ; CHECK-LABEL: @merge_load_i32_ptr32( ; CHECK: load <2 x i32> -; CHECK: [[ELT1:%[0-9]+]] = extractelement <2 x i32> %{{[0-9]+}}, i32 1 +; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i32 1 ; CHECK: inttoptr i32 [[ELT1]] to i8 addrspace(3)* define void @merge_load_i32_ptr32(i32 addrspace(3)* nocapture %a) #0 { entry: @@ -120,7 +120,7 @@ entry: ; CHECK-LABEL: @merge_load_ptr32_i32( ; CHECK: load <2 x i32> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i32> %{{[0-9]+}}, i32 0 +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i32 0 ; CHECK: inttoptr i32 [[ELT0]] to i8 addrspace(3)* define void @merge_load_ptr32_i32(i32 addrspace(3)* nocapture %a) #0 { entry: @@ -134,7 +134,7 @@ entry: } ; CHECK-LABEL: @merge_store_ptr32_i32( -; CHECK: [[ELT0:%[0-9]+]] = ptrtoint i8 addrspace(3)* %ptr0 to i32 +; CHECK: [[ELT0:%[^ ]+]] = ptrtoint i8 addrspace(3)* %ptr0 to i32 ; CHECK: insertelement <2 x i32> undef, i32 [[ELT0]], i32 0 ; CHECK: store <2 x i32> define void @merge_store_ptr32_i32(i32 addrspace(3)* nocapture %a, i8 addrspace(3)* %ptr0, i32 %val1) #0 { @@ -149,8 +149,8 @@ entry: } ; CHECK-LABEL: @merge_store_i32_ptr32( -; CHECK: [[ELT1:%[0-9]+]] = ptrtoint i8 addrspace(3)* %ptr1 to i32 -; CHECK: insertelement <2 x i32> %{{[0-9]+}}, i32 [[ELT1]], i32 1 +; CHECK: [[ELT1:%[^ ]+]] = ptrtoint i8 addrspace(3)* %ptr1 to i32 +; CHECK: insertelement <2 x i32> %{{[^ ]+}}, i32 [[ELT1]], i32 1 ; CHECK: store <2 x i32> define void @merge_store_i32_ptr32(i8 addrspace(3)* addrspace(3)* nocapture %a, i32 %val0, i8 addrspace(3)* %ptr1) #0 { entry: @@ -241,9 +241,9 @@ entry: ; CHECK-LABEL: @merge_load_ptr64_f64( ; CHECK: load <2 x i64> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 0 -; CHECK: [[ELT0_INT:%[0-9]+]] = inttoptr i64 [[ELT0]] to i8 addrspace(1)* -; CHECK: [[ELT1_INT:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 1 +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0 +; CHECK: [[ELT0_INT:%[^ ]+]] = inttoptr i64 [[ELT0]] to i8 addrspace(1)* +; CHECK: [[ELT1_INT:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1 ; CHECK: bitcast i64 [[ELT1_INT]] to double define void @merge_load_ptr64_f64(double addrspace(1)* nocapture %a) #0 { entry: @@ -258,9 +258,9 @@ entry: ; CHECK-LABEL: @merge_load_f64_ptr64( ; CHECK: load <2 x i64> -; CHECK: [[ELT0:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 0 +; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0 ; CHECK: bitcast i64 [[ELT0]] to double -; CHECK: [[ELT1:%[0-9]+]] = extractelement <2 x i64> %{{[0-9]+}}, i32 1 +; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1 ; CHECK: inttoptr i64 [[ELT1]] to i8 addrspace(1)* define void @merge_load_f64_ptr64(double addrspace(1)* nocapture %a) #0 { entry: @@ -274,10 +274,10 @@ entry: } ; CHECK-LABEL: @merge_store_ptr64_f64( -; CHECK: [[ELT0_INT:%[0-9]+]] = ptrtoint i8 addrspace(1)* %ptr0 to i64 +; CHECK: [[ELT0_INT:%[^ ]+]] = ptrtoint i8 addrspace(1)* %ptr0 to i64 ; CHECK: insertelement <2 x i64> undef, i64 [[ELT0_INT]], i32 0 -; CHECK: [[ELT1_INT:%[0-9]+]] = bitcast double %val1 to i64 -; CHECK: insertelement <2 x i64> %{{[0-9]+}}, i64 [[ELT1_INT]], i32 1 +; CHECK: [[ELT1_INT:%[^ ]+]] = bitcast double %val1 to i64 +; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i32 1 ; CHECK: store <2 x i64> define void @merge_store_ptr64_f64(double addrspace(1)* nocapture %a, i8 addrspace(1)* %ptr0, double %val1) #0 { entry: @@ -291,10 +291,10 @@ entry: } ; CHECK-LABEL: @merge_store_f64_ptr64( -; CHECK: [[ELT0_INT:%[0-9]+]] = bitcast double %val0 to i64 +; CHECK: [[ELT0_INT:%[^ ]+]] = bitcast double %val0 to i64 ; CHECK: insertelement <2 x i64> undef, i64 [[ELT0_INT]], i32 0 -; CHECK: [[ELT1_INT:%[0-9]+]] = ptrtoint i8 addrspace(1)* %ptr1 to i64 -; CHECK: insertelement <2 x i64> %{{[0-9]+}}, i64 [[ELT1_INT]], i32 1 +; CHECK: [[ELT1_INT:%[^ ]+]] = ptrtoint i8 addrspace(1)* %ptr1 to i64 +; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i32 1 ; CHECK: store <2 x i64> define void @merge_store_f64_ptr64(i8 addrspace(1)* addrspace(1)* nocapture %a, double %val0, i8 addrspace(1)* %ptr1) #0 { entry: