From: Geert Uytterhoeven Date: Wed, 13 Apr 2022 17:24:08 +0000 (+0200) Subject: pinctrl: renesas: sh7734: Optimize fixed-width reserved fields X-Git-Tag: v6.1-rc5~1223^2~18^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3a0a3c1be88780c720220fed2159bcd255a60ba9;p=platform%2Fkernel%2Flinux-starfive.git pinctrl: renesas: sh7734: Optimize fixed-width reserved fields Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 161 bytes. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be --- diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c index 54f60b3..106a500 100644 --- a/drivers/pinctrl/renesas/pfc-sh7734.c +++ b/drivers/pinctrl/renesas/pfc-sh7734.c @@ -1805,16 +1805,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, FN_IP9_21_20, GP_4_0_FN, FN_IP9_19_18 )) }, - { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP( - 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ + { PINMUX_CFG_REG_VAR("GPSR5", 0xFFFC0018, 32, + GROUP(-20, 1, 1, -6, 1, 1, 1, 1), + GROUP( + /* GP5_31_12 RESERVED */ GP_5_11_FN, FN_IP10_29_28, GP_5_10_FN, FN_IP10_27_26, - 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */ - 0, 0, 0, 0, /* 5, 4 */ + /* GP5_9_4 RESERVED */ GP_5_3_FN, FN_IRQ3_B, GP_5_2_FN, FN_IRQ2_B, GP_5_1_FN, FN_IP11_3, @@ -2352,10 +2349,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4))) }, - { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP( - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ + { PINMUX_CFG_REG_VAR("INOUTSEL5", 0xffc45004, 32, + GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_12 RESERVED */ GP_5_11_IN, GP_5_11_OUT, GP_5_10_IN, GP_5_10_OUT, GP_5_9_IN, GP_5_9_OUT,