From: Tom Stellard Date: Fri, 27 Jul 2012 18:54:46 +0000 (+0000) Subject: radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo X-Git-Tag: accepted/2.0alpha-wayland/20121114.171706~917 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3a0187b1b53eca3143286a5ae7917cd71117b902;p=profile%2Fivi%2Fmesa.git radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo --- diff --git a/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp b/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp index ad48335..69bda63 100644 --- a/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp @@ -16,9 +16,35 @@ using namespace llvm; -AMDGPURegisterInfo::AMDGPURegisterInfo(AMDGPUTargetMachine &tm, +AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii) -: AMDILRegisterInfo(tm, tii), +: AMDGPUGenRegisterInfo(0), TM(tm), TII(tii) { } + +//===----------------------------------------------------------------------===// +// Function handling callbacks - Functions are a seldom used feature of GPUS, so +// they are not supported at this time. +//===----------------------------------------------------------------------===// + +const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister; + +const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + return &CalleeSavedReg; +} + +void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, + int SPAdj, + RegScavenger *RS) const { + assert(!"Subroutines not supported yet"); +} + +unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { + assert(!"Subroutines not supported yet"); + return 0; +} + +#define GET_REGINFO_TARGET_DESC +#include "AMDGPUGenRegisterInfo.inc" diff --git a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h index 5863807..326610d 100644 --- a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h +++ b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h @@ -15,26 +15,46 @@ #ifndef AMDGPUREGISTERINFO_H_ #define AMDGPUREGISTERINFO_H_ -#include "AMDILRegisterInfo.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/Target/TargetRegisterInfo.h" + +#define GET_REGINFO_HEADER +#define GET_REGINFO_ENUM +#include "AMDGPUGenRegisterInfo.inc" namespace llvm { class AMDGPUTargetMachine; class TargetInstrInfo; -struct AMDGPURegisterInfo : public AMDILRegisterInfo +struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { - AMDGPUTargetMachine &TM; + TargetMachine &TM; const TargetInstrInfo &TII; + static const uint16_t CalleeSavedReg; - AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii); + AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii); - virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; + virtual BitVector getReservedRegs(const MachineFunction &MF) const { + assert(!"Unimplemented"); return BitVector(); + } /// getISARegClass - rc is an AMDIL reg class. This function returns the /// ISA reg class that is equivalent to the given AMDIL reg class. - virtual const TargetRegisterClass * - getISARegClass(const TargetRegisterClass * rc) const = 0; + virtual const TargetRegisterClass * getISARegClass( + const TargetRegisterClass * rc) const { + assert(!"Unimplemented"); return NULL; + } + + virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const { + assert(!"Unimplemented"); return NULL; + } + + const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const; + void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, + RegScavenger *RS) const; + unsigned getFrameRegister(const MachineFunction &MF) const; + }; } // End namespace llvm diff --git a/src/gallium/drivers/radeon/AMDIL.h b/src/gallium/drivers/radeon/AMDIL.h index 4029f27..635ff00 100644 --- a/src/gallium/drivers/radeon/AMDIL.h +++ b/src/gallium/drivers/radeon/AMDIL.h @@ -104,8 +104,6 @@ extern Target TheAMDILTarget; extern Target TheAMDGPUTarget; } // end namespace llvm; -#define GET_REGINFO_ENUM -#include "AMDGPUGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "AMDGPUGenInstrInfo.inc" diff --git a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp index 91e0efa..7906363 100644 --- a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp +++ b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp @@ -12,7 +12,6 @@ #include "AMDIL.h" #include "AMDILInstrInfo.h" -#include "AMDILRegisterInfo.h" #include "AMDILUtilityFunctions.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SmallVector.h" @@ -296,10 +295,10 @@ public: ~CFGStructurizer(); /// Perform the CFG structurization - bool run(FuncT &Func, PassT &Pass, const AMDILRegisterInfo *tri); + bool run(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri); /// Perform the CFG preparation - bool prepare(FuncT &Func, PassT &Pass, const AMDILRegisterInfo *tri); + bool prepare(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri); private: void orderBlocks(); @@ -403,7 +402,7 @@ private: BlockInfoMap blockInfoMap; LoopLandInfoMap loopLandInfoMap; SmallVector orderedBlks; - const AMDILRegisterInfo *TRI; + const AMDGPURegisterInfo *TRI; }; //template class CFGStructurizer @@ -420,7 +419,7 @@ template CFGStructurizer::~CFGStructurizer() { template bool CFGStructurizer::prepare(FuncT &func, PassT &pass, - const AMDILRegisterInfo * tri) { + const AMDGPURegisterInfo * tri) { passRep = &pass; funcRep = &func; TRI = tri; @@ -509,7 +508,7 @@ bool CFGStructurizer::prepare(FuncT &func, PassT &pass, template bool CFGStructurizer::run(FuncT &func, PassT &pass, - const AMDILRegisterInfo * tri) { + const AMDGPURegisterInfo * tri) { passRep = &pass; funcRep = &func; TRI = tri; @@ -2634,7 +2633,7 @@ public: protected: TargetMachine &TM; const TargetInstrInfo *TII; - const AMDILRegisterInfo *TRI; + const AMDGPURegisterInfo *TRI; public: AMDILCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL); @@ -2650,7 +2649,7 @@ private: AMDILCFGStructurizer::AMDILCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL) : MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()), - TRI(static_cast(tm.getRegisterInfo()) + TRI(static_cast(tm.getRegisterInfo()) ) { } diff --git a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp index df0ac75..ebd7b26 100644 --- a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp +++ b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// #include "AMDGPUISelLowering.h" // For AMDGPUISD +#include "AMDGPURegisterInfo.h" #include "AMDILDevices.h" #include "AMDILUtilityFunctions.h" #include "llvm/ADT/ValueMap.h" diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index 4e225c2..411c434 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -13,9 +13,9 @@ //===----------------------------------------------------------------------===// #include "AMDILISelLowering.h" +#include "AMDGPURegisterInfo.h" #include "AMDILDevices.h" #include "AMDILIntrinsicInfo.h" -#include "AMDILRegisterInfo.h" #include "AMDILSubtarget.h" #include "AMDILUtilityFunctions.h" #include "llvm/CallingConv.h" diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp index 953b1a9..5dc8664 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp @@ -32,7 +32,7 @@ AMDILInstrInfo::AMDILInstrInfo(TargetMachine &tm) TM(tm) { } -const AMDILRegisterInfo &AMDILInstrInfo::getRegisterInfo() const { +const AMDGPURegisterInfo &AMDILInstrInfo::getRegisterInfo() const { return RI; } diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.h b/src/gallium/drivers/radeon/AMDILInstrInfo.h index 94b0006..551c546 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.h @@ -14,7 +14,7 @@ #ifndef AMDILINSTRUCTIONINFO_H_ #define AMDILINSTRUCTIONINFO_H_ -#include "AMDILRegisterInfo.h" +#include "AMDGPURegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #define GET_INSTRINFO_HEADER @@ -27,7 +27,7 @@ namespace llvm { //class AMDILTargetMachine; class AMDILInstrInfo : public AMDGPUGenInstrInfo { private: - const AMDILRegisterInfo RI; + const AMDGPURegisterInfo RI; TargetMachine &TM; bool getNextBranchInstr(MachineBasicBlock::iterator &iter, MachineBasicBlock &MBB) const; @@ -38,7 +38,7 @@ public: // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As // such, whenever a client has an instance of instruction info, it should // always be able to get register info as well (through this method). - const AMDILRegisterInfo &getRegisterInfo() const; + const AMDGPURegisterInfo &getRegisterInfo() const; bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const; diff --git a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp b/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp deleted file mode 100644 index 76545a5..0000000 --- a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp +++ /dev/null @@ -1,162 +0,0 @@ -//===- AMDILRegisterInfo.cpp - AMDIL Register Information -------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the AMDIL implementation of the TargetRegisterInfo class. -// -//===----------------------------------------------------------------------===// - -#include "AMDILRegisterInfo.h" -#include "AMDIL.h" -#include "AMDILInstrInfo.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" - -using namespace llvm; - -AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm, - const TargetInstrInfo &tii) -: AMDGPUGenRegisterInfo(0), // RA??? - TM(tm), TII(tii) -{ - baseOffset = 0; - nextFuncOffset = 0; -} - -const uint16_t* -AMDILRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const -{ - static const uint16_t CalleeSavedRegs[] = { 0 }; - // TODO: Does IL need to actually have any callee saved regs? - // I don't think we do since we can just use sequential registers - // Maybe this would be easier if every function call was inlined first - // and then there would be no callee issues to deal with - //TODO(getCalleeSavedRegs); - return CalleeSavedRegs; -} - -BitVector -AMDILRegisterInfo::getReservedRegs(const MachineFunction &MF) const -{ - BitVector Reserved(getNumRegs()); - // We reserve the first getNumRegs() registers as they are the ones passed - // in live-in/live-out - // and therefor cannot be killed by the scheduler. This works around a bug - // discovered - // that was causing the linearscan register allocator to kill registers - // inside of the - // function that were also passed as LiveIn registers. - for (unsigned int x = 0, y = 256; x < y; ++x) { - Reserved.set(x); - } - return Reserved; -} - -BitVector -AMDILRegisterInfo::getAllocatableSet(const MachineFunction &MF, - const TargetRegisterClass *RC = NULL) const -{ - BitVector Allocatable(getNumRegs()); - Allocatable.clear(); - return Allocatable; -} - -const TargetRegisterClass* const* -AMDILRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const -{ - static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 }; - // TODO: Keep in sync with getCalleeSavedRegs - //TODO(getCalleeSavedRegClasses); - return CalleeSavedRegClasses; -} -void -AMDILRegisterInfo::eliminateCallFramePseudoInstr( - MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const -{ - MBB.erase(I); -} - -// For each frame index we find, we store the offset in the stack which is -// being pushed back into the global buffer. The offset into the stack where -// the value is stored is copied into a new register and the frame index is -// then replaced with that register. -void -AMDILRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, - RegScavenger *RS) const -{ - assert(!"Implement"); -} - -void -AMDILRegisterInfo::processFunctionBeforeFrameFinalized( - MachineFunction &MF) const -{ - //TODO(processFunctionBeforeFrameFinalized); - // Here we keep track of the amount of stack that the current function - // uses so - // that we can set the offset to the end of the stack and any other - // function call - // will not overwrite any stack variables. - // baseOffset = nextFuncOffset; - MachineFrameInfo *MFI = MF.getFrameInfo(); - - for (uint32_t x = 0, y = MFI->getNumObjects(); x < y; ++x) { - int64_t size = MFI->getObjectSize(x); - if (!(size % 4) && size > 1) { - nextFuncOffset += size; - } else { - nextFuncOffset += 16; - } - } -} -unsigned int -AMDILRegisterInfo::getRARegister() const -{ - return AMDGPU::RA; -} - -unsigned int -AMDILRegisterInfo::getFrameRegister(const MachineFunction &MF) const -{ - return AMDGPU::FP; -} - -unsigned int -AMDILRegisterInfo::getEHExceptionRegister() const -{ - assert(0 && "What is the exception register"); - return 0; -} - -unsigned int -AMDILRegisterInfo::getEHHandlerRegister() const -{ - assert(0 && "What is the exception handler register"); - return 0; -} - -int64_t -AMDILRegisterInfo::getStackSize() const -{ - return nextFuncOffset - baseOffset; -} - -#define GET_REGINFO_TARGET_DESC -#include "AMDGPUGenRegisterInfo.inc" - diff --git a/src/gallium/drivers/radeon/AMDILRegisterInfo.h b/src/gallium/drivers/radeon/AMDILRegisterInfo.h deleted file mode 100644 index 1be001c..0000000 --- a/src/gallium/drivers/radeon/AMDILRegisterInfo.h +++ /dev/null @@ -1,95 +0,0 @@ -//===- AMDILRegisterInfo.h - AMDIL Register Information Impl ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -// This file contains the AMDIL implementation of the TargetRegisterInfo class. -// -//===----------------------------------------------------------------------===// - -#ifndef AMDILREGISTERINFO_H_ -#define AMDILREGISTERINFO_H_ - -#include "llvm/Target/TargetRegisterInfo.h" - -#define GET_REGINFO_HEADER -#include "AMDGPUGenRegisterInfo.inc" -// See header file for explanation - -namespace llvm -{ - - class TargetInstrInfo; - class Type; - - /// DWARFFlavour - Flavour of dwarf regnumbers - /// - namespace DWARFFlavour { - enum { - AMDIL_Generic = 0 - }; - } - - struct AMDILRegisterInfo : public AMDGPUGenRegisterInfo - { - TargetMachine &TM; - const TargetInstrInfo &TII; - - AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii); - /// Code Generation virtual methods... - const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const; - - const TargetRegisterClass* const* - getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; - - BitVector - getReservedRegs(const MachineFunction &MF) const; - BitVector - getAllocatableSet(const MachineFunction &MF, - const TargetRegisterClass *RC) const; - - void - eliminateCallFramePseudoInstr( - MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; - void - eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS = NULL) const; - - void - processFunctionBeforeFrameFinalized(MachineFunction &MF) const; - - // Debug information queries. - unsigned int - getRARegister() const; - - unsigned int - getFrameRegister(const MachineFunction &MF) const; - - // Exception handling queries. - unsigned int - getEHExceptionRegister() const; - unsigned int - getEHHandlerRegister() const; - - int64_t - getStackSize() const; - - virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) - const { - return AMDGPU::GPRI32RegisterClass; - } - private: - mutable int64_t baseOffset; - mutable int64_t nextFuncOffset; - }; - -} // end namespace llvm - -#endif // AMDILREGISTERINFO_H_ diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index d6e80d1..1f59a25 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -28,7 +28,6 @@ CPP_SOURCES := \ AMDILISelLowering.cpp \ AMDILNIDevice.cpp \ AMDILPeepholeOptimizer.cpp \ - AMDILRegisterInfo.cpp \ AMDILSIDevice.cpp \ AMDILSubtarget.cpp \ AMDGPUSubtarget.cpp \ diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.h b/src/gallium/drivers/radeon/R600RegisterInfo.h index 4ed831a..f45995d 100644 --- a/src/gallium/drivers/radeon/R600RegisterInfo.h +++ b/src/gallium/drivers/radeon/R600RegisterInfo.h @@ -15,7 +15,7 @@ #define R600REGISTERINFO_H_ #include "AMDGPUTargetMachine.h" -#include "AMDILRegisterInfo.h" +#include "AMDGPURegisterInfo.h" namespace llvm {