From: ebony.zhu@freescale.com Date: Mon, 18 Dec 2006 08:25:15 +0000 (+0800) Subject: u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default X-Git-Tag: v2008.10-rc1~953^2~19 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09;p=platform%2Fkernel%2Fu-boot.git u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu --- diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bfd316c..687fe84 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -41,7 +41,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */