From: Rob Clark Date: Fri, 11 Oct 2019 23:15:44 +0000 (-0700) Subject: freedreno/ir3: fixup register footprint to account for prefetch X-Git-Tag: upstream/19.3.0~784 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=392a309a55cd81055b2994891c7f1d2d1adbdcba;p=platform%2Fupstream%2Fmesa.git freedreno/ir3: fixup register footprint to account for prefetch It is possible that the result of a pre-fs texture fetch is an output (or partially an output) of the FS. Sine the meta:tex_prefetch instructions are dropped before the assembler, we need to account for this when we fixup the register footprint. Signed-off-by: Rob Clark Reviewed-by: Kristian H. Kristensen --- diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index 10980bd..45d8c90 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -107,6 +107,20 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id) v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); } } + + for (i = 0; i < v->num_sampler_prefetch; i++) { + unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1; + int32_t regid = v->sampler_prefetch[i].dst + n; + if (v->sampler_prefetch[i].half_precision) { + if (gpu_id < 500) { + v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2); + } else { + v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); + } + } else { + v->info.max_reg = MAX2(v->info.max_reg, regid); + } + } } /* wrapper for ir3_assemble() which does some info fixup based on