From: Weili Qian Date: Fri, 14 Jul 2023 11:41:38 +0000 (+0800) Subject: crypto: hisilicon/hpre - enable sva error interrupt event X-Git-Tag: v6.6.17~4031^2~85 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=391dde6e48ff84687395a0a4e84f7e1540301e4e;p=platform%2Fkernel%2Flinux-rpi.git crypto: hisilicon/hpre - enable sva error interrupt event Enable sva error interrupt event. When an error occurs on the sva module, the device reports an abnormal interrupt to the driver. Signed-off-by: Weili Qian Signed-off-by: Herbert Xu --- diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c index 5d0adfb..39297ce 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -209,7 +209,7 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37}, {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37}, {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, - {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xFFFFFE}, + {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE}, {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE}, {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE}, {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, @@ -276,6 +276,9 @@ static const struct hpre_hw_error hpre_hw_errors[] = { .int_msk = BIT(23), .msg = "sva_fsm_timeout_int_set" }, { + .int_msk = BIT(24), + .msg = "sva_int_set" + }, { /* sentinel */ } };