From: Sylwester Nawrocki Date: Tue, 12 May 2020 18:47:14 +0000 (+0200) Subject: pci: Add some PCI Express capability register offset definitions X-Git-Tag: accepted/tizen/unified/20200528.132817~10 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=38b80775375dcdbca833d546ac945d94639e74f1;p=platform%2Fkernel%2Fu-boot.git pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne Signed-off-by: Marek Szyprowski Change-Id: I7ebba592cfe787bffeb0985ada38f11b721166f7 --- diff --git a/include/pci.h b/include/pci.h index d54d3ba..00caeef 100644 --- a/include/pci.h +++ b/include/pci.h @@ -475,11 +475,20 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ +#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Include the ID list */