From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 4 Jul 2022 16:16:26 +0000 (+0200)
Subject: arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order
X-Git-Tag: v6.1-rc5~784^2~30^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3896b8f09271403b641ce09de6b5362fbd622430;p=platform%2Fkernel%2Flinux-starfive.git

arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order

The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.

Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be
---

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 81d178e..28fbf7b 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -55,16 +55,16 @@
 		function = "i2c4";
 	};
 
-	scif3_pins: scif3 {
-		groups = "scif3_data", "scif3_ctrl";
-		function = "scif3";
-	};
-
 	scif0_pins: scif0 {
 		groups = "scif0_data", "scif0_ctrl";
 		function = "scif0";
 	};
 
+	scif3_pins: scif3 {
+		groups = "scif3_data", "scif3_ctrl";
+		function = "scif3";
+	};
+
 	scif_clk_pins: scif_clk {
 		groups = "scif_clk";
 		function = "scif_clk";
@@ -76,16 +76,16 @@
 	status = "okay";
 };
 
-&scif3 {
-	pinctrl-0 = <&scif3_pins>;
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";
 
 	uart-has-rtscts;
 	status = "okay";
 };
 
-&scif0 {
-	pinctrl-0 = <&scif0_pins>;
+&scif3 {
+	pinctrl-0 = <&scif3_pins>;
 	pinctrl-names = "default";
 
 	uart-has-rtscts;