From: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Mon, 5 Dec 2022 13:03:36 +0000 (+0100)
Subject: riscv: attr: Synchronize comments with code
X-Git-Tag: upstream/13.1.0~2339
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3895dd7675197167789e3b346057be417eede943;p=platform%2Fupstream%2Fgcc.git

riscv: attr: Synchronize comments with code

The comment above the enumeration of existing attributes got out of
order and a few entries were forgotten.
This patch synchronizes the comments according to the list.
This commit does not include any functional change.

gcc/ChangeLog:

	* config/riscv/riscv.md: Sync comments with code.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index df57e2b..a8bb331 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -220,7 +220,6 @@
 ;; mfc		transfer from coprocessor
 ;; const	load constant
 ;; arith	integer arithmetic instructions
-;; auipc	integer addition to PC
 ;; logical      integer logical instructions
 ;; shift	integer shift instructions
 ;; slt		set less than instructions
@@ -236,9 +235,13 @@
 ;; fcvt		floating point convert
 ;; fsqrt	floating point square root
 ;; multi	multiword sequence (or user asm statements)
+;; auipc	integer addition to PC
+;; sfb_alu  SFB ALU instruction
 ;; nop		no operation
 ;; ghost	an instruction that produces no real code
 ;; bitmanip	bit manipulation instructions
+;; rotate   rotation instructions
+;; atomic   atomic instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read