From: Colin LeMahieu <colinl@codeaurora.org>
Date: Tue, 18 Nov 2014 21:51:51 +0000 (+0000)
Subject: [Hexagon] Adding A2_sub instruction
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=38765e6d89aa7c83eae34c7ad0cab351a90bc5b6;p=platform%2Fupstream%2Fllvm.git

[Hexagon] Adding A2_sub instruction
Renaming test files.

llvm-svn: 222263
---

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 3acefd5..f06c1dc 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -162,6 +162,7 @@ multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
 
 let isCodeGenOnly = 0 in
 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
+defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
 
 // Pats for instruction selection.
 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
@@ -169,6 +170,7 @@ class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
         (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
 
 def: BinOp32_pat<add, A2_add, i32>;
+def: BinOp32_pat<sub, A2_sub, i32>;
 
 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
                        bit isPredNew> {
diff --git a/llvm/test/MC/Hexagon/instructions.ll b/llvm/test/MC/Hexagon/inst_add.ll
similarity index 100%
rename from llvm/test/MC/Hexagon/instructions.ll
rename to llvm/test/MC/Hexagon/inst_add.ll
diff --git a/llvm/test/MC/Hexagon/inst_sub.ll b/llvm/test/MC/Hexagon/inst_sub.ll
new file mode 100644
index 0000000..7523aa6
--- /dev/null
+++ b/llvm/test/MC/Hexagon/inst_sub.ll
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i32 @foo (i32 %a, i32 %b)
+{
+  %1 = sub i32 %a, %b
+  ret i32 %1
+}
+
+; CHECK:  0000 004021f3 00c09f52
\ No newline at end of file