From: Tom Rini Date: Fri, 26 May 2017 15:19:27 +0000 (-0400) Subject: Merge git://git.denx.de/u-boot-fsl-qoriq X-Git-Tag: v2017.07-rc1~189 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=380e86f361e4e2aef83295972863654fde157560;hp=-c;p=platform%2Fkernel%2Fu-boot.git Merge git://git.denx.de/u-boot-fsl-qoriq --- 380e86f361e4e2aef83295972863654fde157560 diff --combined arch/arm/Kconfig index 2a3a36e,2db7e3c..91f50b0 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -281,7 -281,6 +281,7 @@@ choic config ARCH_AT91 bool "Atmel AT91" + select SPL_BOARD_INIT if SPL config TARGET_EDB93XX bool "Support edb93xx" @@@ -503,7 -502,6 +503,7 @@@ config TARGET_BCM28155_A config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7 + imply CMD_HASH config TARGET_BCMNSP bool "Support bcmnsp" @@@ -555,7 -553,6 +555,7 @@@ config ARCH_KEYSTON config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL imply FIT @@@ -657,7 -654,7 +657,7 @@@ config ARCH_SUNX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT if GENERIC_MMC + imply SPL_MMC_SUPPORT if MMC imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT @@@ -677,7 -674,6 +677,7 @@@ config ARCH_ZYN select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_BOARD_INIT if SPL select SPL_OF_CONTROL if SPL select DM select DM_ETH @@@ -705,7 -701,6 +705,7 @@@ config ARCH_ZYNQM select DM_SERIAL select SUPPORT_SPL select CLK + select SPL_BOARD_INIT if SPL select SPL_CLK select DM_USB if USB @@@ -786,6 -781,20 +786,20 @@@ config TARGET_LS2080ARD development platform that supports the QorIQ LS2080A Layerscape Architecture processor. + config TARGET_LS2081ARDB + bool "Support ls2081ardb" + select ARCH_LS2080A + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + select SUPPORT_SPL + select ARCH_MISC_INIT + help + Support for Freescale LS2081ARDB platform. + The LS2081A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2081A/LS2041A + Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@@ -948,7 -957,6 +962,7 @@@ config ARCH_UNIPHIE select OF_CONTROL select OF_LIBFDT select PINCTRL + select SPL_BOARD_INIT if SPL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL diff --combined arch/arm/dts/Makefile index e2c2584,55f4ae9..2b1a4e9 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@@ -149,7 -149,6 +149,7 @@@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.d dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_arria10_socdk_sdmmc.dtb \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_mcvevk.dtb \ @@@ -175,7 -174,9 +175,9 @@@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-q ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ - fsl-ls2080a-rdb.dtb + fsl-ls2080a-rdb.dtb \ + fsl-ls2081a-rdb.dtb \ + fsl-ls2088a-rdb-qspi.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ @@@ -346,8 -347,7 +348,8 @@@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk. imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb -dtb-$(CONFIG_MX7) += imx7-colibri.dtb +dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ + imx7d-sdb.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --combined include/configs/ls1012a_common.h index 561b81a,861cbc3..bd9b0d3 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@@ -55,9 -55,8 +55,8 @@@ #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION - #define CONFIG_SPI_FLASH_BAR - #define FSL_QSPI_FLASH_SIZE (1 << 24) + #define FSL_QSPI_FLASH_SIZE SZ_64M #define FSL_QSPI_FLASH_NUM 2 /* @@@ -85,6 -84,7 +84,6 @@@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* Command line configuration */ -#define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS #define CONFIG_SYS_HZ 1000 diff --combined include/configs/ls1021aqds.h index a27d70e,5fcaf85..8cf4eaa --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@@ -69,7 -69,7 +69,7 @@@ unsigned long get_board_ddr_clk(void) #endif #ifdef CONFIG_QSPI_BOOT - #define CONFIG_SYS_TEXT_BASE 0x40010000 + #define CONFIG_SYS_TEXT_BASE 0x40100000 #endif #ifdef CONFIG_NAND_BOOT @@@ -402,6 -402,7 +402,6 @@@ /*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@@ -497,7 -498,7 +497,7 @@@ #define CONFIG_FSL_DEVICE_DISABLE - #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 + #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ @@@ -548,14 -549,14 +548,14 @@@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_SD_BOOT) - #define CONFIG_ENV_OFFSET 0x100000 + #define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_IS_IN_NAND @@@ -563,13 -564,19 +563,13 @@@ #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif #define CONFIG_MISC_INIT_R -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --combined include/configs/ls1021atwr.h index 60c3d5d,2a20dec..f0033b8 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@@ -40,6 -40,7 +40,6 @@@ /*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@@ -132,7 -133,7 +132,7 @@@ #endif #ifdef CONFIG_QSPI_BOOT - #define CONFIG_SYS_TEXT_BASE 0x40010000 + #define CONFIG_SYS_TEXT_BASE 0x40100000 #endif #ifndef CONFIG_SYS_TEXT_BASE @@@ -408,7 -409,7 +408,7 @@@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif - #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 + #define CONFIG_SYS_QE_FW_ADDR 0x60940000 /* * Environment @@@ -416,24 -417,30 +416,24 @@@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_SD_BOOT) - #define CONFIG_ENV_OFFSET 0x100000 + #define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x20000 #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_OFFSET 0x100000 + #define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif #define CONFIG_MISC_INIT_R -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --combined include/configs/ls1043a_common.h index b35f96d,05419fe..1b0106d --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@@ -174,6 -174,9 +174,6 @@@ #endif /* Command line configuration */ -#ifndef SPL_NO_ENV -#define CONFIG_CMD_ENV -#endif /* MMC */ #ifndef SPL_NO_MMC @@@ -205,20 -208,20 +205,20 @@@ #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_NAND_BOOT - /* Store Fman ucode at offeset 0x160000(11 blocks). */ + /* Store Fman ucode at offeset 0x900000(72 blocks). */ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND - #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) + #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SD_BOOT) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 1MB (2040 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). + * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC - #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH - #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 + #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 @@@ -226,7 -229,7 +226,7 @@@ #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ - #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 + #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@@ -298,4 -301,10 +298,4 @@@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS1043A_COMMON_H */ diff --combined include/configs/ls1046a_common.h index 1fbafaa,47a544c..b66b8ac --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@@ -138,7 -138,20 +138,17 @@@ #define CONFIG_SYS_I2C_MXC_I2C3 #define CONFIG_SYS_I2C_MXC_I2C4 + /* PCIe */ + #define CONFIG_PCIE1 /* PCIE controller 1 */ + #define CONFIG_PCIE2 /* PCIE controller 2 */ + #define CONFIG_PCIE3 /* PCIE controller 3 */ + + #ifdef CONFIG_PCI + #define CONFIG_PCI_SCAN_SHOW + #define CONFIG_CMD_PCI + #endif + /* Command line configuration */ -#ifndef SPL_NO_ENV -#define CONFIG_CMD_ENV -#endif /* MMC */ #ifndef SPL_NO_MMC @@@ -163,23 -176,23 +173,23 @@@ /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC - #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH - #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 + #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 #define CONFIG_ENV_SPI_MODE 0x03 #elif defined(CONFIG_NAND_BOOT) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND - #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) + #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR - #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 + #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@@ -227,4 -240,10 +237,4 @@@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS1046A_COMMON_H */ diff --combined include/configs/ls2080a_common.h index 285e48d,7b73139..b044768 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@@ -1,4 -1,5 +1,5 @@@ /* + * Copyright 2017 NXP * Copyright (C) 2014 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@@ -28,6 -29,12 +29,12 @@@ #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif + #else + #define CONFIG_SYS_TEXT_BASE 0x20100000 + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ + #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 #endif #define CONFIG_SUPPORT_RAW_INITRD @@@ -160,6 -167,7 +167,6 @@@ unsigned long long get_qixis_addr(void) #endif /* Command line configuration */ -#define CONFIG_CMD_ENV /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) @@@ -185,18 -193,18 +192,18 @@@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581200000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "console=ttyAMA0,38400n8\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" - #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ + #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" @@@ -229,4 -237,10 +236,4 @@@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS2_COMMON_H */ diff --combined include/configs/ls2080aqds.h index dc52b22,84e9db2..d0b0aa9 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@@ -1,4 -1,5 +1,5 @@@ /* + * Copyright 2017 NXP * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@@ -262,15 -263,9 +263,9 @@@ unsigned long get_board_ddr_clk(void) #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 - #if defined(CONFIG_QSPI_BOOT) - #define CONFIG_SYS_TEXT_BASE 0x20010000 - #define CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ - #define CONFIG_ENV_SECT_SIZE 0x10000 - #else + #ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) + #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif @@@ -332,6 -327,7 +327,6 @@@ /* EEPROM */ #define CONFIG_ID_EEPROM -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@@ -363,14 -359,14 +358,14 @@@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=esbc_validate 0x580c80000;" \ - "esbc_validate 0x580cc0000;" \ - "fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + "mcinitcmd=esbc_validate 0x580700000;" \ + "esbc_validate 0x580740000;" \ + "fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@@ -380,12 -376,12 +375,12 @@@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" #endif /* CONFIG_SECURE_BOOT */ diff --combined include/configs/ls2080ardb.h index 2e0d95e,c20a7f4..2dab065 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@@ -1,4 -1,5 +1,5 @@@ /* + * Copyright 2017 NXP * Copyright 2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ @@@ -12,6 -13,14 +13,14 @@@ #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 + #ifdef CONFIG_FSL_QSPI + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_QIXIS_I2C_ACCESS + #endif + #define CONFIG_SYS_I2C_EARLY_INIT + #define CONFIG_DISPLAY_BOARDINFO_LATE + #endif + #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 #define CONFIG_VOL_MONITOR_IR36021_READ @@@ -69,6 -78,7 +78,7 @@@ unsigned long get_board_sys_clk(void) #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) + #ifndef CONFIG_FSL_QSPI /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) @@@ -157,7 -167,6 +167,6 @@@ #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - #define CONFIG_FSL_QIXIS /* use common QIXIS code */ #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f @@@ -242,7 -251,7 +251,7 @@@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #define CONFIG_ENV_IS_IN_FLASH - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) + #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif @@@ -250,12 -259,31 +259,31 @@@ /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL - + #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_FSL_QIXIS /* use common QIXIS code */ + #define QIXIS_QMAP_MASK 0x07 + #define QIXIS_QMAP_SHIFT 5 + #define QIXIS_LBMAP_DFLTBANK 0x00 + #define QIXIS_LBMAP_QSPI 0x00 + #define QIXIS_RCW_SRC_QSPI 0x62 + #define QIXIS_LBMAP_ALTBANK 0x20 + #define QIXIS_RST_CTL_RESET 0x31 + #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 + #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 + #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + #define QIXIS_LBMAP_MASK 0x0f + #define QIXIS_RST_CTL_RESET_EN 0x30 + #endif + /* * I2C */ + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + #endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@@ -263,21 -291,37 +291,36 @@@ #define I2C_MUX_CH_DEFAULT 0x8 /* SPI */ - #ifdef CONFIG_FSL_DSPI + #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH - #define CONFIG_SPI_FLASH_BAR + #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_STMICRO #endif + #ifdef CONFIG_FSL_QSPI + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_SPI_FLASH_STMICRO + #else + #define CONFIG_SPI_FLASH_SPANSION + #endif + #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ + #define FSL_QSPI_FLASH_NUM 2 + #endif + #endif /* * RTC configuration */ #define RTC + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_RTC_PCF8563 1 + #define CONFIG_SYS_I2C_RTC_ADDR 0x51 + #else #define CONFIG_RTC_DS3231 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 + #endif /* EEPROM */ #define CONFIG_ID_EEPROM -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@@ -334,15 -378,34 +377,34 @@@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=esbc_validate 0x580c80000;" \ - "esbc_validate 0x580cc0000;" \ - "fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=esbc_validate 0x580700000;" \ + "esbc_validate 0x580740000;" \ + "fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" \ + BOOTENV + #else + #ifdef CONFIG_QSPI_BOOT + #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21000000\0" \ + "mcmemsize=0x40000000\0" \ + "mcinitcmd=fsl_mc start mc 0x20a00000" \ + " 0x20e00000 \0" \ BOOTENV #else #define CONFIG_EXTRA_ENV_SETTINGS \ @@@ -358,15 -421,16 +420,16 @@@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581100000\0" \ + "kernel_start=0x581000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" \ BOOTENV #endif + #endif #undef CONFIG_BOOTARGS @@@ -376,11 -440,18 +439,18 @@@ " hugepagesz=2m hugepages=256" #undef CONFIG_BOOTCOMMAND + #ifdef CONFIG_QSPI_BOOT + /* Try to boot an on-QSPI kernel first, then do normal distro boot */ + #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \ + " && bootm $kernel_start" \ + " || run distro_bootcmd" + #else /* Try to boot an on-NOR kernel first, then do normal distro boot */ - #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ + #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \ " && cp.b $kernel_start $kernel_load $kernel_size" \ " && bootm $kernel_load" \ " || run distro_bootcmd" + #endif /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET @@@ -389,7 -460,11 +459,11 @@@ #define CONFIG_PHY_CORTINA #define CONFIG_PHYLIB #define CONFIG_SYS_CORTINA_FW_IN_NOR - #define CONFIG_CORTINA_FW_ADDR 0x581000000 + #ifdef CONFIG_QSPI_BOOT + #define CONFIG_CORTINA_FW_ADDR 0x20980000 + #else + #define CONFIG_CORTINA_FW_ADDR 0x580980000 + #endif #define CONFIG_CORTINA_FW_LENGTH 0x40000 #define CORTINA_PHY_ADDR1 0x10